Abstract: A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.

Abstract: A semiconductor device includes a plurality of signal lines which are arranged at a predetermined pitch; first and second MOS transistors which are connected to the signal lines, and also serially connected to each other; and a connection device which functions as a connection node between the serially-connected first and second MOS transistors, and connects a source area of one of the first and second MOS transistors to a drain area of the other of the first and second MOS transistors via contact holes, which are formed through an insulating layer, and a conduction layer connected to the contact holes.

Abstract: A semiconductor device prevents the ON current of a complementary field effect transistor from varying with changes in ambient temperature. The semiconductor device includes: a buffer circuit that generates a power-supply voltage of a CMOS; a first replica transistor that is a replica of a p-channel MOS transistor forming the CMOS, and is diode-connected; a second replica transistor that is a replica of an n-channel MOS transistor forming the CMOS, and is diode-connected; and a voltage controller that controls the voltage between the anode and cathode of the replica transistors so that the current value of the current flowing into the replica transistor becomes equal to a given target value. In this semiconductor device, the buffer circuit generates the power-supply voltage, with the target voltage being a voltage that is controlled by the voltage controller.

Abstract: A semiconductor device prevents the OFF current of a complementary field effect transistor from varying with changes in ambient temperature. The semiconductor device includes: a substrate voltage generating circuit that generates the substrate voltage of an n-channel MOS transistor forming a CMOS; a replica transistor that is a replica of the n-channel MOS transistor, and is diode-connected; and a voltage applier that applies a voltage of a predetermined voltage value between the anode and cathode of the replica transistor. In this semiconductor device, the substrate voltage of the replica transistor is the substrate voltage generated by the substrate voltage generating circuit. The substrate voltage generating circuit controls the substrate voltage to be generated so that the current value of the current flowing into the replica transistor becomes equal to a given target value.

Abstract: To include a memory cell array that stores therein data in a reversible manner, an antifuse circuit that stores therein data in a nonvolatile manner, a sense amplifier array that temporarily holds data that is read from the memory cell array of data to be written in the memory cell array, and a control circuit that performs a control for writing the data held in the sense amplifier array in the antifuse circuit. According to the present invention, it is not required to provide any dedicated latch circuit for each antifuse element. Therefore, a writing process of writing data in the antifuse circuit can be performed at high speed without causing an increase of the chip dimension due to a dedicated latch circuit.

Abstract: To provide a semiconductor device including: a MOS transistor formed in a semiconductor substrate and have a threshold voltage to be adjusted, a replica transistor of the MOS transistor, a monitoring circuit monitors a gate/source voltage needed when the replica transistor flows a current having a given designed value, a negative voltage pumping circuit generates a substrate voltage of the MOS transistor, based on an output from the monitoring circuit, and a limiting circuit defines the operation of the negative voltage pumping circuit, regardless of a monitoring result of the monitoring circuit, in response to an excess of the substrate voltage with respect to a predetermined value.

Abstract: In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.

Abstract: A voltage control circuit of the present invention is applicable to a combination of a decoder circuit and a level conversion circuit connected to the decoder circuit. The voltage control circuit includes a level conversion circuit voltage line for applying a voltage to the level conversion circuit, and a boost voltage connection switch for switching a voltage applied to the level conversion circuit voltage line according to an output signal from the decoder circuit. This configuration makes it possible to prevent, when a boost voltage is applied to the level conversion circuit, the breakdown of transistors in the level conversion circuit due to a ripple in the boost voltage.

Abstract: An initializing circuit initializing a semiconductor memory device includes a command generating circuit generating a mode register set command in response to a reset command signal, a mode register set control circuit producing a reset signal in response to the mode register set command, and a bank active control circuit resetting the semiconductor memory device by generating an all-bank precharge command in response to the reset signal.

Abstract: A semiconductor device includes a plurality of signal lines which are arranged at a predetermined pitch; first and second MOS transistors which are connected to the signal lines, and also serially connected to each other; and a connection device which functions as a connection node between the serially-connected first and second MOS transistors, and connects a source area of one of the first and second MOS transistors to a drain area of the other of the first and second MOS transistors via contact holes, which are formed through an insulating layer, and a conduction layer connected to the contact holes.

Abstract: An anti-fuse circuit according to the present invention includes an anti-fuse element that holds data in a nonvolatile manner and a latch circuit that temporarily holds data to be written to the anti-fuse element. The writing to the latch circuit can be performed in the order of nanoseconds, and thus, even when the defective addresses respectively different are written in a plurality of chips, a writing process to the latch circuit can be completed in a very short period of time. Thereby, an actual process for writing to the anti-fuse element can be performed in parallel for the chips, and as a result, the process for writing to the anti-fuse element can be performed at high speed.

Abstract: A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.

Abstract: A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.

Abstract: A semiconductor device comprises one or more elements subjected to trimming, formed on a main surface side of a silicon substrate and that is/are to be laser trimmed, and an electrode lead of the element subjected to trimming disposed below the position of the element subjected to trimming. The electrode lead subjected to trimming comprises a diffusion layer formed in an uppermost layer of the silicon substrate. The diffusion layer is covered with a protection film made of doped polysilicon and is directly formed on the silicon substrate.

Abstract: In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.

Abstract: A semiconductor memory device having high integration, low consumption power and high operation speed compatible to each other including a sense amplifier circuit having plural pull-down circuits and a pull-up circuit, in which a transistor constituting one of plural pull-down circuits has a larger constant than that of a transistor constituting other pull-down circuits, for example, a channel length and a channel width, a pull-down circuit having a larger constant of the transistor in the plural pull-down circuits is precedingly activated and then another pull-down circuit and the pull-up circuit are activated to conduct reading and, further, the data line and the precedingly driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.

Abstract: Inverters are connected between a pseudo power supply wiring and a main power supply wiring, while inverters are connected between a main power supply wiring VDD and a pseudo power supply wiring. Connected to the sources of transistors are switching areas for switching to the main power supply wiring or the pseudo power supply wiring. Connected to the sources of transistors are switching areas for switching to the main power supply wiring or the pseudo power supply wiring. Even if improper connections are found or logical changes are required, the connection destination of the source is switched easily.

Abstract: A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.

Abstract: A voltage control circuit of the present invention is applicable to a combination of a decoder circuit and a level conversion circuit connected to the decoder circuit. The voltage control circuit includes a level conversion circuit voltage line for applying a voltage to the level conversion circuit, and a boost voltage connection switch for switching a voltage applied to the level conversion circuit voltage line according to an output signal from the decoder circuit. This configuration makes it possible to prevent, when a boost voltage is applied to the level conversion circuit, the breakdown of transistors in the level conversion circuit due to a ripple in the boost voltage.

Abstract: A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.