Patents by Inventor Shinichi Miyatake
Shinichi Miyatake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6992343Abstract: A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2F and smaller than 4F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.Type: GrantFiled: October 29, 2004Date of Patent: January 31, 2006Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Elpida Memory, Inc.Inventors: Shinichi Miyatake, Kazuhiko Kajigaya, Kazuyuki Miyazawa, Tomonori Sekiguchi, Riichiro Takemura, Takeshi Sakata
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Patent number: 6925017Abstract: A column select line YS1 can be enabled at the same time as the enabling of a word line. Write data is written from an I/O gate into a selected data line. An adjacent unselected sense amplifier reads data from memory cells. A source node of a cross-coupled sense amplifier connected to each data line pair is divided for each column select line, thereby to prevent a write-selected cross-coupled amplifier from driving the source node. In the write operation, data can be written at a high speed. On the other hand, it becomes possible to prevent a write-sense amplifier from driving the source node. Therefore, adjacent sense amplifiers can achieve stable read operation without being affected from the write-sense amplifier.Type: GrantFiled: November 6, 2003Date of Patent: August 2, 2005Assignees: Hitachi, Ltd., Elpida Memory, Inc., Hitachi ULSI Systems Co., Ltd.Inventors: Riichiro Takemura, Tomonori Sekiguchi, Takeshi Sakata, Shinichi Miyatake, Hiromasa Noda, Kazuhiko Kajigaya
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Patent number: 6882557Abstract: The contact resistance of each switch is reduced, and the on-resistances of all of the switches are set to be uniform, while the area required for arrangement of bit line selection switches is not increased. The switches are connected to one-side ends of the bit lines provided at the odd-numbered positions, and are connected to the other-side ends of the bit lines provided at the even-numbered positions. A pair of odd-numbered or even-numbered bit lines are connected to the terminals of each sense amplifier, respectively. The memory cells are arranged at predetermined intersection points of the word lies and the bit lines, the number of the predetermined intersection points being equal to half of all the intersection points thereof, in such a manner that when one word line is selected, the memory cells connected to the selected word-line can be electrically connected in such a manner that one memory cell is electrically connected to each terminal of the unit circuits.Type: GrantFiled: September 5, 2003Date of Patent: April 19, 2005Inventors: Kazuhiko Kajigaya, Hiromasa Noda, Shinichi Miyatake, Riichiro Takemura, Tomonori Sekiguchi, Takeshi Sakata
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Publication number: 20050056876Abstract: A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6 F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2 F and smaller than 4 F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.Type: ApplicationFiled: October 29, 2004Publication date: March 17, 2005Inventors: Shinichi Miyatake, Kazuhiko Kajigaya, Kazuyuki Miyazawa, Tomonori Sekiguchi, Riichiro Takemura, Takeshi Sakata
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Patent number: 6828612Abstract: A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2F and smaller than 4F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.Type: GrantFiled: March 17, 2003Date of Patent: December 7, 2004Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Elpida Memory, Inc.Inventors: Shinichi Miyatake, Kazuhiko Kajigaya, Kazuyuki Miyazawa, Tomonori Sekiguchi, Riichiro Takemura, Takeshi Sakata
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Publication number: 20040184304Abstract: The contact resistance of each switch is reduced, and the on-resistances of all of the switches are set to be uniform, while the area required for arrangement of bit line selection switches is not increased.Type: ApplicationFiled: September 5, 2003Publication date: September 23, 2004Inventors: Kazuhiko Kajigaya, Hiromasa Noda, Shinichi Miyatake, Riichiro Takemura, Tomonori Sekiguchi, Takeshi Sakata
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Publication number: 20040124440Abstract: A column select line YS1 can be enabled at the same time as the enabling of a word line. Write data is written from an I/O gate into a selected data line. An adjacent unselected sense amplifier reads data from memory cells. A source node of a cross-coupled sense amplifier connected to each data line pair is divided for each column select line, thereby to prevent a write-selected cross-coupled amplifier from driving the source node. In the write operation, data can be written at a high speed. On the other hand, it becomes possible to prevent a write-sense amplifier from driving the source node. Therefore, adjacent sense amplifiers can achieve stable read operation without being affected from the write-sense amplifier.Type: ApplicationFiled: November 6, 2003Publication date: July 1, 2004Inventors: Riichiro Takemura, Tomonori Sekiguchi, Takeshi Sakata, Shinichi Miyatake, Hiromasa Noda, Kazuhiko Kajigaya
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Patent number: 6633508Abstract: Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.Type: GrantFiled: August 28, 2001Date of Patent: October 14, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Masaya Muranaka, Shinichi Miyatake, Yukihide Suzuki, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame
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Publication number: 20030173593Abstract: A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell•two cells/bit method has a twin cell structure employing a one-intersection 6F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2F and smaller than 4F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.Type: ApplicationFiled: March 17, 2003Publication date: September 18, 2003Inventors: Shinichi Miyatake, Kazuhiko Kajigaya, Kazuyuki Miyazawa, Tomonori Sekiguchi, Riichiro Takemura, Takeshi Sakata
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Patent number: 6538946Abstract: P-type well regions Ap1 and Ap9 on which first and second pre-charge circuits are formed, and p-type well regions Ap2, Ap3, Ap7 and ap8 on which first and second Y-switch circuits are formed, are formed on both ends of a sense amplifier formation region, respectively. A bit line BL2T, which extends from a first memory cell formation region of first and second memory cell formation regions arranged in both sides of the sense amplifier formation region, arrives at a p-type well region An1 on which a sense amplifier is formed, via both a p-type well region Ap1 on which the first pre-charge circuit is formed and p-type well regions Ap2 and Ap3 on which the Y-switch circuit is formed. Therefore, a wiring region c for arranging wirings other than bit lines can be secured on the extended bit line BL2T.Type: GrantFiled: July 5, 2001Date of Patent: March 25, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Kouji Arai, Shinichi Miyatake
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Patent number: 6411543Abstract: There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g.Type: GrantFiled: January 8, 2001Date of Patent: June 25, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Seiji Narui, Osamu Nagashima, Masatoshi Hasegawa, Hiroki Fujisawa, Shinichi Miyatake, Tsuyuki Suzuki, Yasunobu Aoki, Tsutom Takahashi, Kazuhiko Kajigaya
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Publication number: 20020031036Abstract: Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.Type: ApplicationFiled: August 28, 2001Publication date: March 14, 2002Inventors: Masaya Muranaka, Shinichi Miyatake, Yukihide Suzuki, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame
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Patent number: 6282141Abstract: Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.Type: GrantFiled: May 15, 2000Date of Patent: August 28, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Masaya Muranaka, Shinichi Miyatake, Yukihide Suzuki, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame
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Publication number: 20010001598Abstract: There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g.Type: ApplicationFiled: January 8, 2001Publication date: May 24, 2001Inventors: Seiji Narui, Osamu Nagashima, Masatoshi Hasegawa, Hiroki Fujisawa, Shinichi Miyatake, Tsuyuki Suzuki, Yasunobu Aoki, Tsutom Takahashi, Kazuhiko Kajigaya
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Patent number: 6201728Abstract: There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g.Type: GrantFiled: February 8, 1999Date of Patent: March 13, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Seiji Narui, Osamu Nagashima, Masatoshi Hasegawa, Hiroki Fujisawa, Shinichi Miyatake, Tsuyuki Suzuki, Yasunobu Aoki, Tsutom Takahashi, Kazuhiko Kajigaya
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Patent number: 6198128Abstract: In a case where an impurity for suppressing the short channel effect of MISFETs is introduced into a semiconductor substrate obliquely to the principal surface thereof, gate electrodes adjacent to each other are arranged so that the impurity to be introduced in directions crossing the gate electrodes may not be introduced into the part of the semiconductor substrate lying between the gate electrodes, and the source region of the MISFETs is arranged in the part between the gate electrodes.Type: GrantFiled: September 7, 1999Date of Patent: March 6, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Hisao Asakura, Yoshitaka Tadaki, Toshihiro Sekiguchi, Ryo Nagai, Masafumi Miyamoto, Masayuki Nakamura, Shinichi Miyatake, Tsuyuki Suzuki, Masahiro Hyoma
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Patent number: 6178108Abstract: In a semiconductor memory device having a plurality of memory cells in which each memory cell is formed of an address selection MOSFET and an information storing capacitor and the plate voltage consisting of an intermediate potential is supplied to the common electrode of the information storing capacitor, the memory access is enabled by detecting indirect that the plate voltage has reached the predetermined potential near the intermediate potential with the voltage detecting circuit or timer circuit, inhibiting the selecting operation of the word lines or precharging the pair bit lines to the intermediate potential when the plate voltage is lower than the predetermined potential, and then canceling the above inhibit condition after the plate voltage has reached the predetermined potential.Type: GrantFiled: February 26, 1999Date of Patent: January 23, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Shinichi Miyatake, Shigekazu Kase, Masayuki Nakamura, Masatoshi Hasegawa, Kazuhiko Kajigaya
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Patent number: 6064605Abstract: Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.Type: GrantFiled: September 14, 1999Date of Patent: May 16, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Masaya Muranaka, Shinichi Miyatake, Yukihide Suzuki, Kanehide Kenmizaki, Makoto Morino, Tetsuya Kitame
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Patent number: 5983358Abstract: A semiconductor memory having a redundancy circuit includes a judgment device for receiving outputs of first ROMs for storing a defective address therein and judging whether or not a defective memory cell and a spare memory cell to replace the defective memory cell belong to the same memory cell, and also includes a timing adjustment circuit for changing the timing of control signals applied to memory mat control circuits according to an output of the judgment device. When the defective and spare memory cells belong to the same memory mat, the timing of the control signals is made fast.Type: GrantFiled: September 26, 1997Date of Patent: November 9, 1999Assignees: Hitachi, Ltd., Hitachi Ulsi Engineering Corp., Hitachi Device Engineering Co., Ltd.Inventors: Masashi Horiguchi, Shinichi Miyatake, Tathunori Mushya, Yasuhiro Kasama, Yoichi Matsuno, Yasushi Kawase, Yoshinobu Nakagome
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Patent number: 5970003Abstract: A semiconductor memory device comprising at least one memory mat comprised of a plurality of memory cells respectively provided at points where a plurality of word lines and spare word lines respectively intersect a plurality of bit lines and spare bit lines placed so as to intersect the word lines and spare word lines. In the semiconductor memory device, a plurality of fuse means allowed to open or remain unopen in accordance with stored information encoded with respect to addresses for specifying defective word lines or defective bit lines are used to control gate means based on their corresponding complementary signals. Thus, the gate means transmit signals for selecting their corresponding word lines or bit lines to thereby produce coincidence/non-coincidence signals.Type: GrantFiled: May 26, 1998Date of Patent: October 19, 1999Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Shinichi Miyatake, Shuuichi Kubouchi