Patents by Inventor Shinichiro Takatani

Shinichiro Takatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6787817
    Abstract: The present invention provides a semiconductor device for high frequency application having a high breakdown voltage and the method of manufacturing thereof. A region including a first conductivity type high impurity concentration semiconductor and a region including a first conductivity type low impurity concentration semiconductor are provided from an ohmic layer side at the side far from a semiconductor substrate of the end surface of a barrier layer opposite the semiconductor substrate and between the ohmic layer and a gate electrode. The sheet impurity concentration of the region including a first conductivity type low impurity concentration semiconductor is set to be lower than that between the bottom surface of the gate electrode at the side of the semiconductor substrate and the end surface of the channel layer opposite the semiconductor substrate.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: September 7, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Hiroyuki Takazawa, Shinichiro Takatani, Masao Yamane, Masayoshi Kobayashi
  • Publication number: 20040063280
    Abstract: The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively acts as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.
    Type: Application
    Filed: June 25, 2003
    Publication date: April 1, 2004
    Inventors: Hiroshi Miki, Keiko Kushida, Yasuhiro Shimamoto, Shinichiro Takatani, Yoshihisa Fujisaki, Hiromi Nakai
  • Patent number: 6653668
    Abstract: It is an object of the present invention to provide a radio frequency module incorporating an MMIC that has a high S/N ratio while ensuring a high output. A radio frequency module according to the present invention incorporates an MMIC having a field effect transistor in which channel layers for traveling of carriers are formed by a heterostructure of two or more different kinds of materials, and height of a potential barrier of an interface between the different kinds of materials is less than 0.22 eV.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: November 25, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Katsuhiko Higuchi, Shinichiro Takatani
  • Patent number: 6635913
    Abstract: The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively act as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: October 21, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Miki, Keiko Kushida, Yasuhiro Shimamoto, Shinichiro Takatani, Yoshihisa Fujisaki, Hiromi Nakai
  • Publication number: 20030168672
    Abstract: The present invention provides a semiconductor device for high frequency application having a high breakdown voltage and the method of manufacturing thereof. A region including a first conductivity type high impurity concentration semiconductor and a region including a first conductivity type low impurity concentration semiconductor are provided from an ohmic layer side at the side far from a semiconductor substrate of the end surface of a barrier layer opposite the semiconductor substrate and between the ohmic layer and a gate electrode. The sheet impurity concentration of the region including a first conductivity type low impurity concentration semiconductor is set to be lower than that between the bottom surface of the gate electrode at the side of the semiconductor substrate and the end surface of the channel layer opposite the semiconductor substrate.
    Type: Application
    Filed: December 13, 2002
    Publication date: September 11, 2003
    Inventors: Hiroyuki Takazawa, Shinichiro Takatani, Masao Yamane, Masayoshi Kobayashi
  • Publication number: 20030006436
    Abstract: It is an object of the present invention to provide a radio frequency module incorporating an MMIC that has a high S/N ratio while ensuring a high output.
    Type: Application
    Filed: August 30, 2002
    Publication date: January 9, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Katsuhiko Higuchi, Shinichiro Takatani
  • Patent number: 6469326
    Abstract: It is an object of the present invention to provide a radio frequency module incorporating an MMIC that has a high S/N ratio while ensuring a high output. A radio frequency module according to the present invention incorporates an MMIC having a field effect transistor in which channel layers for traveling of carriers are formed by a heterostructure of two or more different kinds of materials, and height of a potential barrier of an interface between the different kinds of materials is less than 0.22 eV.
    Type: Grant
    Filed: February 27, 2001
    Date of Patent: October 22, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Katsuhiko Higuchi, Shinichiro Takatani
  • Publication number: 20020140014
    Abstract: A semiconductor device includes a capacitor having a lower electrode (102), a high-dielectric-constant or ferroelectric thin film (103), and an upper electrode (104) which are subsequently stacked. An impurity having an action of suppressing the catalytic activity of a metal or a conductive oxide constituting the electrode is added to the upper electrode (104). The addition of the impurity is effective to prevent inconveniences such as a reduction in capacitance, an insulation failure, and the peeling of the electrode due to hydrogen heat-treatment performed after formation of the upper electrode (104), and to improve the long-term reliability.
    Type: Application
    Filed: February 13, 2002
    Publication date: October 3, 2002
    Inventors: Shinichiro Takatani, Hiroshi Miki, Keiko Kushida, Yoshihisa Fujisaki, Kazuyoshi Torii
  • Publication number: 20020123317
    Abstract: A radio frequency module packaging system and method characterized by compact package size, reduced packaging loss and variation, and reduced heat generation. The radio frequency module is provided with via holes, electrodes for signals, and grounding electrodes on the surface of a substrate. Under the electrodes for signals, via holes are made, and on both sides of the electrodes for signals, grounding via holes are made so that these via holes form microstrip lines. Both input and output ends of a high frequency circuit including an active device, formed as the module's functional circuit on the substrate, are routed through the via holes and connected to another circuit.
    Type: Application
    Filed: June 19, 2001
    Publication date: September 5, 2002
    Inventors: Takuma Tanimoto, Shinichiro Takatani, Hiroshi Kondoh
  • Publication number: 20020115303
    Abstract: A semiconductor device has a strongly bonding structure for improving bond strength between the semiconductor and the insulating layer even if the insulating layer is formed by a traditional method which causes slight damage to the semiconductor. The strongly bonding structure includes an oxide layer 12 (containing a constituent element of the semiconductor), an oxide bonding layer, a bond-creating layer (which may disappear from the finished product), and an insulating layer, which are sequentially formed one over the other. The oxide layer may be either one which occurs naturally or one which is formed artificially. The oxide bonding layer is formed by reaction between oxygen in the oxide layer and a constituent element in the bond-creating layer. The bond-creating layer contains an element that oxidizes and an element that reacts with a constituent element of the insulating layer.
    Type: Application
    Filed: December 13, 2001
    Publication date: August 22, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Hiroshi Ohta, Shinichiro Takatani, Toshimi Yokoyama, Takeshi Kikawa
  • Patent number: 6396092
    Abstract: A semiconductor device includes a capacitor having a lower electrode (102), a high-dielectric-constant or ferroelectric thin film (103), and an upper electrode (104) which are subsequently stacked. An impurity having an action of suppressing the catalytic activity of a metal or a conductive oxide constituting the electrode is added to the upper electrode (104). The addition of the impurity is effective to prevent inconveniences such as a reduction in capacitance, an insulation failure, and the peeling of the electrode due to hydrogen heat-treatment performed after formation of the upper electrode (104), and to improve the long-term reliability.
    Type: Grant
    Filed: September 20, 1999
    Date of Patent: May 28, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Shinichiro Takatani, Hiroshi Miki, Keiko Kushida, Yoshihisa Fujisaki, Kazuyoshi Torii
  • Publication number: 20020056862
    Abstract: The upper electrode of a capacitor is constituted of laminated films which respectively act as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.
    Type: Application
    Filed: December 27, 2001
    Publication date: May 16, 2002
    Inventors: Hiroshi Miki, Keiko Kushida, Yasuhiro Shimamoto, Shinichiro Takatani, Yoshihisa Fujisaki, Hiromi Nakai
  • Publication number: 20020047147
    Abstract: Disclosed is a semiconductor device having ferroelectric capacitors above a principal surface of a substrate and a process for producing the same wherein an oriented polycrystal silicon film or an amorphous silicon film 52 is disposed on the whole area beneath a conductive diffusion barrier, 61 or 73, under a lower electrode, 62 or 74, of each ferroelectric capacitor formed in the device. As a result, the conductive diffusion barrier, the lower electrode and the capacitor ferroelectric film become oriented films; therefore, it is possible to reduce the signal variation in capacitors even in minute semiconductor devices, and obtain a highly reliable semiconductor device.
    Type: Application
    Filed: October 31, 2001
    Publication date: April 25, 2002
    Inventors: Keiko Kushida, Masahiko Hiratani, Kazuyoshi Torii, Shinichiro Takatani, Hiroshi Miki, Yuuichi Matsui, Yoshihisa Fujisaki
  • Patent number: 6342712
    Abstract: The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively act as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.
    Type: Grant
    Filed: August 13, 1999
    Date of Patent: January 29, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Miki, Keiko Kushida, Yasuhiro Shimamoto, Shinichiro Takatani, Yoshihisa Fujisaki, Hiromi Nakai
  • Publication number: 20020000573
    Abstract: It is an object of the present invention to provide a radio frequency module incorporating an MMIC that has a high S/N ratio while ensuring a high output.
    Type: Application
    Filed: February 27, 2001
    Publication date: January 3, 2002
    Inventors: Katsuhiko Higuchi, Shinichiro Takatani
  • Patent number: 6144052
    Abstract: An oriented polycrystal silicon film or an amorphous silicon film 52 is disposed on the whole area beneath a conductive diffusion barrier 61 under a lower electrode of a ferroelectric capacitor. As a result, the conductive diffusion barrier, the lower electrode and the capacitor ferroelectric film become oriented films; therefore, it is possible to reduce the signal variation in capacitors even in minute semiconductor devices, and obtain a highly reliable semiconductor device.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: November 7, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Keiko Kushida, Masahiko Hiratani, Kazuyoshi Torii, Shinichiro Takatani, Hiroshi Miki, Yuuichi Matsui, Yoshihisa Fujisaki
  • Patent number: 5508554
    Abstract: Disclosed is a semiconductor device capable of suppressing the generation of dislocations due to the difference in lattice constant by insertion of one or more defect type compound layers in a semiconductor layered structure. The strain generated by the mismatch of the lattice is relaxed by a large amount of vacancies contained in the defect type compound layer, to suppress the generation and the propagation of dislocations, thus inexpensively fabricating a semiconductor device with less deterioration of the characteristics due to defects with good repeatability.
    Type: Grant
    Filed: August 23, 1994
    Date of Patent: April 16, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Shinichiro Takatani, Takeshi Kikawa, Yoko Uchida
  • Patent number: 5399230
    Abstract: A compound semiconductor is etched by a step of substituting a composite element of a compound semiconductor with other element, thereby forming a compound layer on the surface of the compound semiconductor and a step of removing the compound layer from the surface. Etching depth is controlled not by etching time, but by the number of runs (repetitions) of the etching step, and thus can be precisely controlled.
    Type: Grant
    Filed: June 7, 1993
    Date of Patent: March 21, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Shinichiro Takatani, Takeshi Kikawa, Chushirou Kusano, Masatoshi Nakazawa
  • Patent number: 5373191
    Abstract: Source and drain electrode metals of a field effect transistor having a recessed gate electrode metal are directly connected to a high impurity concentration semiconductor layer which faces the gate electrode metal through an insulator film which defines the side wall of the recess. The source and drain electrode metals may be disposed so as to face the gate electrode metal through the side insulator film. With this arrangement, it is possible to lower the parasitic resistance between the gate electrode and another electrode of the field effect transistor, to lower the contact resistance between a semiconductor layer and the source and drain electrodes, to reduce the capacitance of the recess gate electrode and to increase the source-gate breakdown voltage, advantageously. The above-described arrangement is particularly suitable for a transistor employing a compound semiconductor, and can also be applied to semiconductor devices other than field effect transistors.
    Type: Grant
    Filed: December 30, 1992
    Date of Patent: December 13, 1994
    Assignee: Hitachi Ltd.
    Inventors: Toshiyuki Usagawa, Yoshinori Imamura, Hidekazu Okuhira, Shigeo Goto, Masayoshi Kobayashi, Shinichiro Takatani
  • Patent number: 5181087
    Abstract: Source and drain electrode metals of a field effect transistor having a recessed gate electrode metal are directly connected to a high impurity concentration semiconductor layer which faces the gate electrode metal through an insulator film which defines the side wall of the recess. The source and drain electrode metals may be disposed so as to face the gate electrode metal through the side insulator film. With this arrangement, it is possible to lower the parasitic resistance between the gate electrode and another electrode of the field effect transistor, to lower the contact resistance between a semiconductor layer and the source and drain electrodes, to reduce the capacitance of the recess gate electrode and to increase the source-gate breakdown voltage, advantageously. The above-described arrangement is particularly suitable for a transistor employing a compound semiconductor, and can also be applied to semiconductor devices other than field effect transistors.
    Type: Grant
    Filed: April 19, 1989
    Date of Patent: January 19, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Toshiyuki Usagawa, Yoshinori Imamura, Hidekazu Okuhira, Shigeo Goto, Masayoshi Kobayashi, Shinichiro Takatani