Abstract: An object of the present invention is to provide a compound having an anti-inflammatory activity or a pharmacologically acceptable salt thereof. The solution of the present invention is a compound of general formula (1) or a pharmacologically acceptable salt thereof. wherein the symbols in the formula are defined below: R1: e.g., a C1-C6 alkyl group; R2: a C1-C6 alkyl group; A: e.g., an oxygen atom; and R3: e.g., a C1-C6 alkyl group.

Abstract: This free-cutting copper alloy contains 75.0%-78.5% Cu, 2.95%-3.55% Si, 0.07%-0.28% Sn, 0.06%-0.14% P, and 0.022%-0.25% Pb, with the remainder being made up of Zn and inevitable impurities. The composition satisfies the following relations: 76.2?f1=Cu+0.8×Si?8.5×Sn+P+0.5×Pb?80.3, 61.5?f2=Cu?4.3×Si?0.7×Sn?P+0.5×Pb?63.3. The area ratios (%) of the constituent phases satisfy the following relations: 25???65, 0???1.5, 0???0.2, 0???2.0, 97.0?f3=?+?, 99.4?f4=?+?+?+?, 0?f5=?+??2.5, 27?f6=?+6×?1/2+0.5×??70. The long side of the ? phase does not exceed 40 ?m, the long side of the ? phase does not exceed 25 ?m, and the ? phase is present within the ? phase.

Abstract: A semiconductor device is comprised of a memory cell array with multiple memory cells arranged in a matrix, multiple bit-line pairs provided for each memory cell column in the memory cell array, multiple input/output circuits provided respectively corresponding to the multiple bit-line pairs, and as interface control circuit that controls the data input/output to the multiple input/output circuits when performing the data write and data read for each memory cell row in a normal mode. The interface control circuit is comprised of a selection circuit. When the data write and data read are performed for each memory cell row in a test mode, the selection circuit selects the data input/output to one of first input/output circuit and a second input/output circuit, respectively corresponding to a first memory cell included in the memory cell row and a second memory cell adjoining the first memory cell, according to a test address.

Abstract: This free-cutting copper alloy casting contains 75.0-78.5% Cu, 2.95-3.55% Si, 0.07-0.28% Sn, 0.06-0.14% P, 0.022-0.20% Pb, with the remainder being made up of Zn and unavoidable impurities. The composition satisfies the following relations: 76.2?f1=Cu+0.8×Si?8.5×Sn+P+0.5×Pb?80.3, 61.2?f2=Cu?4.4×Si?0.8×Sn?P+0.5×Pb?62.8. The area ratios (%) of the constituent phases satisfy the following relations: 2.5??65, 0???2.0, 0???0.3, 0???2.0, 96.5?f3=?+?, 99.2?f4=?+?+?+?, 0?f6=?+??3.0, 29?f6=?+6×?1/2+0.5×??66. The long side of the ? phase does not exceed 50 ?m, the long side of the ? phase does not exceed 25 ?m, and the ? phase is present within the ? phase.

Abstract: This free-cutting copper alloy contains 75.0 %-78.5% Cu, 2.95%-3.55% Si, 0.07%-0.28% Sn, 0.06%-0.14% P, and 0.022%-0.25% Pb, with the remainder being made up of Zn and inevitable impurities. The composition satisfies the following relations: 76.2?f1=Cu+0.8×Si?8.5×Sn+P+0.5×Pb?80.3, 61.5?f2=Cu?4.3×Si?0.7×Sn?P+0.5×Pb?63.3. The area ratios (%) of the constituent phases satisfy the following relations: 25???65, 0???1.5, 0???0.2, 0???2.0, 97.0?f3=?+?, 99.4?f4=?+?+?+?, 0?f5=?+??2.5, 27?f6=?+6×?1/2+0.5×??70. The long side of the ? phase does not exceed 40 ?m, the long side of the ? phase does not exceed 25 ?m, and the ? phase is present within the ? phase.

Abstract: An object of the present invention is to provide a compound having an anti-inflammatory activity or a pharmacologically acceptable salt thereof. The solution of the present invention is a compound of general formula (1) or a pharmacologically acceptable salt thereof. wherein the symbols in the formula are defined below: R1: e.g., a C1-C6 alkyl group; R2: a C1-C6 alkyl group; A: e.g., an oxygen atom; and R3: e.g., a C1-C6 alkyl group.

Abstract: A semiconductor memory device including a pair of first bit lines extended in a first direction, a pair of second bit lines extended in the first direction, a first word line extended in a second direction crossing the first direction, a second word line extended in the second direction, a memory cell surrounded by the first bit line, the second bit line, the first word line, and the second word line, and including a drive transistor, a first transfer transistor coupled with one of the pair of first bit lines, and having a gate coupled with the first word line, a second transfer transistor coupled with one of the pair of second bit lines, and having a gate coupled with the second word line, and a load transistor, a write drive circuit that transfers data to the memory cell.

Abstract: To suppress inflow of external air through a rack insertion opening while a sample rack is pulled out. An apparatus includes a housing, a temperature control space, and an air temperature control part. The housing has the rack insertion opening on one side surface for putting in and taking out the sample rack. The air temperature control part has an air intake portion for intake of air in the temperature control space, a fan for blowing air taken in from the air intake portion toward the sample rack accommodated in the temperature control space, and a cooling element provided to cool the air on a path of air taken in from the air intake portion. The air temperature control part is configured to reduce an amount of air flowing near the rack insertion opening while the sample rack is pulled out from the temperature control space as compared to while the sample rack is accommodated in the temperature control space, so as to suppress inflow of air through the rack insertion opening.

Abstract: To suppress generation of dew condensation in temperature control space when heating temperature control is performed. In an apparatus, an air temperature control part for cooling or heating air in temperature control space has a first temperature control element for performing at least cooling of air, and a second temperature control element for performing at least heating of air downstream of the first temperature control element. In this manner, when heating temperature control is performed, cooling and dehumidification of air taken in from an air intake portion can be performed by the first temperature control element, and then heating of the dehumidified air can be performed by the second temperature control element.

Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

Abstract: A parameter selection support system that supports, based on a capacity of a drive device, selection of parameters of an operation pattern and parameters of mechanical condition for a load that is driven by the drive device and includes a display unit that displays an input screen for the parameters, a reception unit that receives the parameters and the capacity, and a controller that calculates an allowable range for each of some of the parameters that is allowable for the capacity received by the reception unit and causes the display unit to display the allowable range on the input screen. The parameters of the operation pattern include a moving amount of the load.

Abstract: The semiconductor device includes a supply circuit for supplying a boosted voltage to a distal end of a wiring driven by a drive signal. The supply circuit includes an inverter circuit having an input coupled to the wiring, and a switch element controlled by an output signal of the inverter circuit. The switch element couples the boosted voltage to the distal end of the wiring.

Abstract: An embodiment of the present invention controls a mobile body device to carry out a natural action. A mobile body control device (1) includes: an image acquiring section (21) configured to acquire an image of a surrounding environment of a specific mobile body device; and a control section (2) which is configured to (i) refer to the image and infer, in accordance with the image, a scene in which the specific mobile body device is located, (ii) determine an action in accordance with the scene inferred, and (iii) control the mobile body device to carry out the action determined.

Abstract: This free-cutting copper alloy casting contains 75.0-78.5% Cu, 2.95-3.55% Si, 0.07-0.28% Sn, 0.06-0.14% P, 0.022-0.20% Pb, with the remainder being made up of Zn and unavoidable impurities. The composition satisfies the following relations: 76.2?f1=Cu+0.8×Si?8.5×Sn+P+0.5×Pb?80.3, 61.2?f2=Cu?4.4×Si?0.8×Sn?P+0.5×Pb?62.8. The area ratios (%) of the constituent phases satisfy the following relations: 2.5??65, 0???2.0, 0???0.3, 0???2.0, 96.5?f3=?+?, 99.2?f4=?+?+?+?, 0?f6=?+??3.0, 29?f6=?+6×?1/2+0.5×??66. The long side of the ? phase does not exceed 50 ?m, the long side of the ? phase does not exceed 25 ?m, and the ? phase is present within the ? phase.

Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

Abstract: This free-cutting copper alloy contains 75.0%-78.5% Cu, 2.95%-3.55% Si, 0.07%-0.28% Sn, 0.06%-0.14% P, and 0.022%-0.25% Pb, with the remainder being made up of Zn and inevitable impurities. The composition satisfies the following relations: 76.2?f1=Cu+0.8×Si?8.5×Sn+P+0.5×Pb?80.3, 61.5?f2=Cu?4.3×Si?0.7×Sn?P+0.5×Pb?63.3. The area ratios (%) of the constituent phases satisfy the following relations: 25???65, 0???1.5, 0???0.2, 0???2.0, 97.0?f3=?+?, 99.4?f4=?+?+?+?, 0?f5=?+??2.5, 27?f6=?+6×?1/2+0.5×??70. The long side of the ? phase does not exceed 40 ?m, the long side of the ? phase does not exceed 25 ?m, and the ? phase is present within the ? phase.

Abstract: This free-cutting copper alloy contains 75.0%-78.5% Cu, 2.95%-3.55% Si, 0.07%-0.28% Sn, 0.06%-0.14% P, and 0.022%-0.25% Pb, with the remainder being made up of Zn and inevitable impurities. The composition satisfies the following relations: 76.2?f1=Cu+0.8×Si?8.5×Sn+P+0.5×Pb?80.3, 61.5?f2=Cu?4.3×Si?0.7×Sn?P+0.5×Pb?63.3. The area ratios (%) of the constituent phases satisfy the following relations: 25???65, 0???1.5, 0???0.2, 0???2.0, , 97.0?f3=?+?, 99.4?f4=?+?+?+?, 0?f5=?+??2.5, 27?f6=?+6×?1/2+0.5×??70. The long side of the ? phase does not exceed 40 ?m, the long side of the ? phase does not exceed 25 ?m, and the ? phase is present within the ? phase.

Abstract: The present invention verifies a method of reducing skin irritation (particularly, cumulative skin irritation) caused by transdermal administration of a local anesthetic using iontophoresis, and provides an electrode pad for relief from a puncture pain which is safe not only at single administration but also at repeated administrations. The electrode pad comprises a base sheet; an electrode placed on the base sheet; an adhesive sheet placed on the base sheet and having an opening, within which the electrode being exposed; and a medicament reservoir containing a local anesthetic and placed in the opening of the adhesive sheet while being in contact with the electrode. An inner peripheral surface of the opening of the adhesive sheet and an outer peripheral surface of the medicament reservoir are prevented from coming into contact with human skin while contacting with each other, and thereby skin irritation is reduced.

Abstract: This free-cutting copper alloy contains more than 77.0% but less than 81.0% Cu, more than 3.4% but less than 4.1% Si, 0.07% to 0.28% Sn, 0.06% to 0.14% P, and more than 0.02% but less than 0.25% Pb, with the remainder being made up of Zn and unavoidable impurities. The composition satisfies the following relations: 1.0?f0=100×Sn/(Cu+Si+0.5×Pb+0.5×P?75.5)?3.7, 78.5?f1=Cu+0.8×Si?8.5×Sn+P+0.5×Pb?83.0, 61.8?f2=Cu?4.2×Si?0.5×Sn?2×P?63.7. The area ratios (%) of the constituent phases satisfy the following relations, 36???72, 0???2.0, 0???0.5, 0???2.0, 96.5?f3=?+?, 99.4?f4=?+?+?+?, 0?f5=?+??3.0, 38?f6=?+6×?1/2+0.5×??80. The long side of the ? phase does not exceed 50 ?m, and the long side of the ? phase does not exceed 25 ?m.

Abstract: A semiconductor storage device having a plurality of low power consumption modes is provided. The semiconductor storage device includes a plurality of memory modules where a plurality of low power consumption modes can be set and cancelled based on a first and a second control signals. At least a part of memory modules of the plurality of memory modules have a propagation path that propagates an inputted first control signal to a post stage memory module. The second control signal is inputted into each of the plurality of memory modules in parallel. Setting and cancelling of the first low power consumption mode of each memory module are performed based on a combination of the first control signal that is propagated through the propagation path and the second control signal.