Patents by Inventor Shinpei Iijima
Shinpei Iijima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8492814Abstract: A method of forming a semiconductor device includes the following processes. A pillar is formed which stands on a semiconductor substrate. A first insulating film is formed which covers a side surface of the pillar. An upper portion of the first insulating film is removed to expose a side surface of an upper portion of the pillar. A contact plug is formed, which contacts the side surface of the upper portion of the pillar and a top surface of the pillar.Type: GrantFiled: August 23, 2012Date of Patent: July 23, 2013Assignee: Elpida Memory, Inc.Inventors: Hiroyuki Fujimoto, Shinpei Iijima
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Publication number: 20120313156Abstract: A method of forming a semiconductor device includes the following processes. A pillar is formed which stands on a semiconductor substrate. A first insulating film is formed which covers a side surface of the pillar. An upper portion of the first insulating film is removed to expose a side surface of an upper portion of the pillar. A contact plug is formed, which contacts the side surface of the upper portion of the pillar and a top surface of the pillar.Type: ApplicationFiled: August 23, 2012Publication date: December 13, 2012Applicant: ELPIDA MEMORY, INC.Inventors: Hiroyuki FUJIMOTO, Shinpei IIJIMA
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Patent number: 8278172Abstract: A method of forming a semiconductor device includes the following processes. A pillar is formed which stands on a semiconductor substrate. A first insulating film is formed which covers a side surface of the pillar. An upper portion of the first insulating film is removed to expose a side surface of an upper portion of the pillar. A contact plug is formed, which contacts the side surface of the upper portion of the pillar and a top surface of the pillar.Type: GrantFiled: August 4, 2010Date of Patent: October 2, 2012Assignee: Elpida Memory, Inc.Inventors: Hiroyuki Fujimoto, Shinpei Iijima
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Publication number: 20110033994Abstract: A method of forming a semiconductor device includes the following processes. A pillar is formed which stands on a semiconductor substrate. A first insulating film is formed which covers a side surface of the pillar. An upper portion of the first insulating film is removed to expose a side surface of an upper portion of the pillar. A contact plug is formed, which contacts the side surface of the upper portion of the pillar and a top surface of the pillar.Type: ApplicationFiled: August 4, 2010Publication date: February 10, 2011Applicant: ELPIDA MEMORY, INC.Inventors: Hiroyuki FUJIMOTO, Shinpei IIJIMA
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Patent number: 7811895Abstract: A stacked capacitor in a memory cell has a bottom electrode made of a metal or metal compound, a capacitor insulation film and a top electrode made of a metal or a metal compound. The capacitor insulation film includes an aluminum oxide film having a thickness of 2 to 4 nm and in contact with the bottom electrode, and an overlying hafnium oxide film having a thickness of 3 to 6 nm. The stacked capacitor has a higher resistance against a biased temperature test.Type: GrantFiled: May 12, 2009Date of Patent: October 12, 2010Assignee: Elpida Memory, Inc.Inventor: Shinpei Iijima
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Patent number: 7700942Abstract: A semiconductor device includes an active area isolated by an isolation area on a semiconductor substrate. A transistor includes a gate electrode extending across the active area, source/drain regions formed in the active area on both sides of the gate electrode, and impurity-containing contact plugs connected to the source/drain regions. The source/drain regions are formed by thermal diffusion of impurities from the impurity-containing contact plugs toward the active area.Type: GrantFiled: June 4, 2008Date of Patent: April 20, 2010Assignee: Elpida Memory, Inc.Inventor: Shinpei Iijima
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Patent number: 7667257Abstract: Method for solving the problem caused when forming a crown-structure capacitor in a trench which is formed in an insulating film, and having difficulty in electrical by connecting a first upper electrode formed on the inside wall of the trench and a second upper electrode which is to be a plate because of the intervention of dielectric between the first and second upper electrodes. The conducting state of the first upper electrode and the plate upper electrode is ensured by utilizing a tantalum oxide film formed on a titanium nitride film, which is brought to a completely conducting state when heat treated. A crown structure is formed without removing the insulating film, in which a trench has been formed, by wet etching, whereby a stacked trench capacitor, which has double the capacity is provided while eliminating the collapse of the lower electrode or pair bit defect.Type: GrantFiled: October 24, 2006Date of Patent: February 23, 2010Assignee: Elpida Memory, Inc.Inventor: Shinpei Iijima
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Publication number: 20090221127Abstract: A stacked capacitor in a memory cell has a bottom electrode made of a metal or metal compound, a capacitor insulation film and a top electrode made of a metal or a metal compound. The capacitor insulation film includes an aluminum oxide film having a thickness of 2 to 4 nm and in contact with the bottom electrode, and an overlying hafnium oxide film having a thickness of 3 to 6 nm. The stacked capacitor has a higher resistance against a biased temperature test.Type: ApplicationFiled: May 12, 2009Publication date: September 3, 2009Applicant: ELPIDA MEMORY, INC.Inventor: Shinpei IIJIMA
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Publication number: 20090197384Abstract: According to an aspect of the present invention, there is provided a semiconductor memory device. The semiconductor memory device is provided with an insulator and a capacitor. The capacitor is provided with a lower electrode provided with an inner portion and an outer portion, a dielectric portion on the lower electrode, and an upper electrode on the dielectric portion. The inner portion is provided with a lower part and an upper part upwardly extending from the lower part. The insulator laterally holds the lower part. The outer portion is arranged on the insulator and is electrically connected with the upper part.Type: ApplicationFiled: April 15, 2009Publication date: August 6, 2009Applicant: ELPIDA MEMORY, INC.Inventor: Shinpei IIJIMA
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Patent number: 7498601Abstract: A phase-change memory device has a phase-change layer, a heater electrode having an end held in contact with the phase-change layer, a contact plug of different kinds of material having a first electrically conductive material plug made of a first electrically conductive material and held in contact with the other end of the heater electrode, and a second electrically conductive material plug made of a second electrically conductive material having a specific resistance smaller than the first electrically conductive material, the first electrically conductive material plug and the second electrically conductive material plug being stacked in one contact hole, the heater electrode and the second electrically conductive material plug being held in contact with each other in overlapping relation to each other, and an electrically conductive layer electrically connected to the second electrically conductive material plug.Type: GrantFiled: November 27, 2006Date of Patent: March 3, 2009Assignee: Elpida Memory, Inc.Inventors: Tsutomu Hayakawa, Shinpei Iijima
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Publication number: 20080296666Abstract: A semiconductor device includes an active area isolated by an isolation area on a semiconductor substrate. A transistor includes a gate electrode extending across the active area, source/drain regions formed in the active area on both sides of the gate electrode, and impurity-containing contact plugs connected to the source/drain regions.Type: ApplicationFiled: June 4, 2008Publication date: December 4, 2008Applicant: ELPIDA MEMORY, INC.Inventor: Shinpei IIJIMA
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Patent number: 7382014Abstract: A semiconductor device with a capacitor includes a lower electrode, a dielectric and an upper electrode on the dielectric layer. The dielectric layer including more than one polycrystalline tantalum oxide layer and more than one separation layer, wherein the polycrystalline tantalum oxide layers and the separation layers are alternately stacked, while one of the polycrystalline tantalum oxide layers is a lowermost layer among the stacked layers.Type: GrantFiled: May 17, 2006Date of Patent: June 3, 2008Assignee: Elpida Memory, Inc.Inventor: Shinpei Iijima
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Patent number: 7259058Abstract: A ruthenium electrode with a low amount of oxygen contamination and high thermal stability is formed by a chemical vapor deposition method. In the chemical vapor deposition method using an organoruthenium compound as a precursor, the introduction of an oxidation gas is limited to when the precursor is supplying, and the reaction is allowed to occur at a low oxygen partial pressure. Consequently, it is possible to form a ruthenium film with a low amount of oxygen contamination. Further, after formation of the ruthenium film, annealing at not less than the formation temperature is performed, thereby forming a ruthenium film with high thermal stability.Type: GrantFiled: December 18, 2001Date of Patent: August 21, 2007Assignee: Renesas Techonology Corp.Inventors: Yasuhiro Shimamoto, Masahiko Hiratani, Yuichi Matsui, Satoshi Yamamoto, Toshihide Nabatame, Toshio Ando, Hiroshi Sakuma, Shinpei Iijima
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Publication number: 20070120106Abstract: A phase-change memory device has a phase-change layer, a heater electrode having an end held in contact with the phase-change layer, a contact plug of different kinds of material having a first electrically conductive material plug made of a first electrically conductive material and held in contact with the other end of the heater electrode, and a second electrically conductive material plug made of a second electrically conductive material having a specific resistance smaller than the first electrically conductive material, the first electrically conductive material plug and the second electrically conductive material plug being stacked in one contact hole, the heater electrode and the second electrically conductive material plug being held in contact with each other in overlapping relation to each other, and an electrically conductive layer electrically connected to the second electrically conductive material plug.Type: ApplicationFiled: November 27, 2006Publication date: May 31, 2007Inventors: Tsutomu HAYAKAWA, Shinpei Iijima
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Publication number: 20070108493Abstract: The present invention aims at solving the problem caused when forming a crown-structure capacitor in a trench which is formed in an insulating film, in particular, the problem of having difficulty in electrical connecting a first upper electrode formed on the inside wall of the trench and a second upper electrode which is to be a plate because of the intervention of dielectric between the first upper electrode and the second upper electrode. To solve the above problem, the conducting state of the first upper electrode and the plate upper electrode is ensured by utilizing the characteristic of a tantalum oxide film formed on a titanium nitride film, which is brought to the completely conducting state when it is heat treated.Type: ApplicationFiled: October 24, 2006Publication date: May 17, 2007Applicant: ELPIDA MEMORY, INC.Inventor: Shinpei Iijima
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Patent number: 7183170Abstract: After an upper electrode protective film is formed such that it is in a firm contact with ruthenium film of the upper electrode without damaging the ruthenium film, the upper electrode is etched, thereby, a MIM capacitor is obtained in which leak current is not increased due to oxidation of the ruthenium film of the upper electrode.Type: GrantFiled: November 30, 2004Date of Patent: February 27, 2007Assignee: Elpida Memory, Inc.Inventors: Yoshitaka Nakamura, Tsuyoshi Kawagoe, Hiroshi Sakuma, Isamu Asano, Keiji Kuroki, Hidekazu Goto, Shinpei Iijima
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Publication number: 20060234510Abstract: According to an aspect of the present invention, there is provided a semiconductor memory device. The semiconductor memory device is provided with an insulator and a capacitor. The capacitor is provided with a lower electrode provided with an inner portion and an outer portion, a dielectric portion on the lower electrode, and an upper electrode on the dielectric portion. The inner portion is provided with a lower part and an upper part upwardly extending from the lower part. The insulator laterally holds the lower part. The outer portion is arranged on the insulator and is electrically connected with the upper part.Type: ApplicationFiled: April 12, 2006Publication date: October 19, 2006Inventor: Shinpei Iijima
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Patent number: 7074669Abstract: A semiconductor integrated circuit device includes a plurality of capacitor elements, which are separated from each other by a first insulating film on a plane. Each of the plurality of capacitor elements has a lower electrode, a dielectric film, and an upper electrode, and the lower electrode has a crown structure. At least one of the lower electrode and the upper electrode has a laminate structure composed of a plurality of conductive films. An outermost film of the laminate structure on a side of the dielectric film is a ruthenium film, and a portion of the laminate structure other than the outermost film has higher selective growth than the first insulating film with respect to the ruthenium film. Here, the first insulating film is desirably a tantalum oxide film.Type: GrantFiled: May 22, 2003Date of Patent: July 11, 2006Assignee: Elpida Memory,Inc.Inventors: Shinpei Iijima, Hiroshi Sakuma
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Patent number: 7071071Abstract: A lower electrode of a capacitor element is formed by manufacturing a crown structure while using a first conducting material such as titanium nitride or the like excellent in mechanical strength as a base material and by forming a film of a second conducting material such as ruthenium or the like, which is comparatively difficult to be oxidized, on a surface of the crown structure. First, ruthenium is deposited on a surface of the crown structure by using a sputtering method. Thereafter, the ruthenium (sputtered ruthenium) placed in a peripheral region of the crown structure is removed by etching, and a film of ruthenium is further formed on a surface of the crown structure by using a CVD method while using the sputtered ruthenium as a seed layer.Type: GrantFiled: March 16, 2004Date of Patent: July 4, 2006Assignee: Elpida Memory, Inc.Inventors: Shinpei Iijima, Keiji Kuroki
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Publication number: 20060102983Abstract: A stacked capacitor in a memory cell has a bottom electrode made of a metal or metal compound, a capacitor insulation film and a top electrode made of a metal or a metal compound. The capacitor insulation film includes an aluminum oxide film having a thickness of 2 to 4 nm and in contact with the bottom electrode, and an overlying hafnium oxide film having a thickness of 3 to 6 nm. The stacked capacitor has a higher resistance against a biased temperature test.Type: ApplicationFiled: November 8, 2005Publication date: May 18, 2006Applicant: ELPIDA MEMORY, INC.Inventor: Shinpei Iijima