Patents by Inventor Shinpei Iijima

Shinpei Iijima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030107073
    Abstract: A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.
    Type: Application
    Filed: December 18, 2002
    Publication date: June 12, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Shinpei Iijima, Yuzuru Ohji, Masato Kunitomo, Masahiko Hiratani, Yuichi Matsui, Hiroyuki Ohta, Yukihiro Kumagai
  • Patent number: 6576946
    Abstract: Capacitors are stretched over a plurality of memory cells in the direction of a bit line in order to effectively utilize spaces between adjacent cells. In addition, by creating a cubic structure of each capacitor by adoption of a self-matching technique, the structure can be utilized more effectively. As a result, it is possible to assure a sufficient capacitor capacitance in spite of a limitation imposed by the fabrication technology and obtain an assurance of sufficient space between cells in a shrunk area of a memory cell accompanying high-scale integration and miniaturization of a semiconductor device.
    Type: Grant
    Filed: July 20, 1999
    Date of Patent: June 10, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Misuzu Kanai, Yuzuru Ohji, Takuya Fukuda, Shinpei Iijima, Ryouichi Furukawa, Yasuhiro Sugawara, Hideharu Yahata
  • Patent number: 6544835
    Abstract: There is provided a technique for forming an Ru film on the bottom of a deep hole with a considerable film thickness for the lower electrode of an information storage capacity element in order to improve the yield of manufacturing DRAMs. The Ru film is formed on the side wall and the bottom of a deep hole as material for preparing the lower electrode of an information storage capacity element to be produced there under the condition of a gasification flow rate ratio of the raw materials ((Ru(C2H5C5H4)2/O2) is not less than 10% Then, the ratio of the film thickness of the Ru film on the bottom “b” of the hole to the largest film thickness “a” of the Ru film in the hole is not less than 50%.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: April 8, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Satoshi Yamamoto, Shinpei Iijima
  • Patent number: 6544834
    Abstract: An integrated semiconductor device has an improved reliability and is adapted to a higher degree of integration without reducing the accumulated electric charge of each information storage capacity element. The semiconductor device is provided with a DRAM having memory cells, each comprising an information storage capacity element C connected in series to a memory cell selection MISFET Qs formed on a main surface of a semiconductor substrate 1 and having a lower electrode 54, a capacity insulating film 58 and an upper electrode 59. The lower electrode 54 is made of ruthenium film oriented in a particular plane bearing, e.g., a (002) plane, and the capacity insulating film 58 is made of a polycrystalline tantalum film obtained by thermally treating an amorphous tantalum oxide film containing crystal of tantalum oxide in an as-deposited state for crystallization.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: April 8, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiro Sugawara, Shinpei Iijima, Yuzuru Oji, Naruhiko Nakanishi, Misuzu Kanai, Masahiko Hiratani
  • Patent number: 6534375
    Abstract: A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: March 18, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Shinpei Iijima, Yuzuru Ohji, Masato Kunitomo, Masahiko Hiratani, Yuichi Matsui, Hiroyuki Ohta, Yukihiro Kumagai
  • Publication number: 20030045067
    Abstract: In a semiconductor integrated circuit device according to the present invention, a polycrystalline silicon film is formed along an inner wall of a trench in which a capacitor is to be formed, and the polycrystalline silicon film and a lower electrode is contacted to each other on the entire inner wall of the trench. Therefore, oxygen permeated into the lower electrode at the time of a thermal treatment of a tantalum oxide film is consumed at an interface between the polycrystalline silicon film and the lower electrode. Thus, the oxygen does not reach the surface of the plug, so that such a disadvantage can be prevented that the oxygen permeated through the lower electrode causes the oxidation on the surface of the silicon plug below the lower electrode to form a high-resistance oxide layer when a dielectric film formed on a lower electrode of a capacitor of a DRAM is subjected to a thermal treatment in an oxygen atmosphere.
    Type: Application
    Filed: August 29, 2002
    Publication date: March 6, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Shinpei Iijima, Hiroshi Sakuma
  • Publication number: 20030041803
    Abstract: A semiconductor device includes a DRAM having a memory cell constructed by an information storage capacitor C which is comprised of a lower electrode 54 made of a ruthenium film and an upper electrode 62 made of a capacity insulating film 61 and a titanium nitride film and which is connected in series with a memory cell selection MISFET Qs formed on the main surface of a semiconductor substrate 1. The capacity insulating film 61 is made of a multi layered film comprising two layered crystallized tantalum oxide films 56 and 58 each having a film thickness of 10 nm or less. The film thickness of the capacity insulating film 61 is set to 10 to 40 nm.
    Type: Application
    Filed: October 15, 2002
    Publication date: March 6, 2003
    Inventors: Masato Kunitomo, Shinpei Iijima
  • Publication number: 20030038325
    Abstract: A first silicon film is so formed as to extend along the inner surface of trenches 52 formed in a silicon oxide film 50, an oxide film is formed on the surface of the first silicon film, and a second amorphous silicon film is further deposited. Heat-treatment is applied to the surface of the second amorphous silicon film for seeding silicon nuclei and for promoting grain growth, and a granular silicon crystal 57 is grown from the second amorphous silicon film. In this way, the resistance of a lower electrode 59 of a capacitance device can be lowered.
    Type: Application
    Filed: October 17, 2002
    Publication date: February 27, 2003
    Inventors: Yasuhiro Sugawara, Ryouichi Furukawa, Toshio Uemura, Akira Takamatsu, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Shinpei Iijima, Yuzuru Ohji
  • Publication number: 20020160566
    Abstract: There is provided a technique for forming an Ru film on the bottom of a deep hole with a considerable film thickness for the lower electrode of an information storage capacity element in order to improve the yield of manufacturing DRAMs. The Ru film is formed on the side wall and the bottom of a deep hole as material for preparing the lower electrode of an information storage capacity element to be produced there under the condition of a gasification flow rate ratio of the raw materials ((Ru(C2H5C5H4)2/O2) is not less than 10% Then, the ratio of the film thickness of the Ru film on the bottom “b” of the hole to the largest film thickness “a” of the Ru film in the hole is not less than 50%.
    Type: Application
    Filed: June 18, 2002
    Publication date: October 31, 2002
    Inventors: Satoshi Yamamoto, Shinpei Iijima
  • Patent number: 6423593
    Abstract: There is provided a technique for forming an Ru film on the bottom of a deep hole with a considerable film thickness for the lower electrode of an information storage capacity element in order to improve the yield of manufacturing DRAMs. The Ru film is formed on the side wall and the bottom of a deep hole as material for preparing the lower electrode of an information storage capacity element to be produced there under the condition of a gasification flow rate ratio of the raw materials ((Ru(C2H5C5H4)2/O2) is not less than 10%. Then, the ratio of the film thickness of the Ru film on the bottom “b” of the hole to the largest film thickness “a” of the Ru film in the hole is not less than 50%.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: July 23, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Satoshi Yamamoto, Shinpei Iijima
  • Publication number: 20020047152
    Abstract: There is provided a technique for forming an Ru film on the bottom of a deep hole with a considerable film thickness for the lower electrode of an information storage capacity element in order to improve the yield of manufacturing DRAMs. The Ru film is formed on the side wall and the bottom of a deep hole as material for preparing the lower electrode of an information storage capacity element to be produced there under the condition of a gasification flow rate ratio of the raw materials ((Ru(C2H5C5H4)2 /O2) is not less than 10%. Then, the ratio of the film thickness of the Ru film on the bottom “b” of the hole to the largest film thickness “a” of the Ru film in the hole is not less than 50%.
    Type: Application
    Filed: August 31, 2001
    Publication date: April 25, 2002
    Inventors: Satoshi Yamamoto, Shinpei Iijima
  • Publication number: 20020045310
    Abstract: A technique is provided which is capable of forming a Ru film constituting a lower electrode of an information storing capacitive element in an aperture with high precision.
    Type: Application
    Filed: August 31, 2001
    Publication date: April 18, 2002
    Inventors: Shinpei Iijima, Satoshi Yamamoto
  • Publication number: 20020022357
    Abstract: A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.
    Type: Application
    Filed: August 8, 2001
    Publication date: February 21, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Shinpei Iijima, Yuzuru Ohji, Masato Kunitomo, Masahiko Hiratani, Yuichi Matsui, Hiroyuki Ohta, Yukihiro Kumagai
  • Publication number: 20020014646
    Abstract: The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode 18 adjacent an insulating region 26. This base electrode 18 can comprise either polysilicon or a metal. A layer 28 of a first material, such as a siliciding metal, is formed over the base electrode 18 as well as the adjacent insulating region. A self-aligned capacitor electrode 12 can then be formed by reacting the first material 28 with the base electrode 18 and removing unreacted portions of the first material 28 from the insulating region 26. The capacitor is then completed by forming a dielectric layer 16 over the self-aligned capacitor electrode 12 and a second capacitor electrode 14 over the dielectric layer 16.
    Type: Application
    Filed: July 30, 2001
    Publication date: February 7, 2002
    Inventors: Robert Tsu, Isamu Asano, Shinpei Iijima, William R. McKee
  • Publication number: 20010050389
    Abstract: A semiconductor device equipped with information storage capacitor comprising a first capacitor electrode, an oxide film, a second capacitor electrode and insulating films containing silicon as a main constituting element, wherein at least one of first and second capacitor electrodes contains as a main constituting element at least one element selected from rhodium, ruthenium, iridium, osmium and platinum, and as an adding element at least one element selected from palladium, nickel, cobalt and titanium, is excellent in adhesiveness between the capacitor electrodes and the insulating films.
    Type: Application
    Filed: March 8, 2001
    Publication date: December 13, 2001
    Inventors: Hiroshi Moriya, Tomio Iwasaki, Hiroyuki Ohta, Shinpei Iijima, Isamu Asano, Yuzuru Ohji, Yoshitaka Nakamura
  • Publication number: 20010038114
    Abstract: Plug electrodes of silicon are formed being buried in the through holes in a first insulating film, the plug electrodes being electrically connected to the source and drain regions of a MISFET on the main surface of a semiconductor substrate. Then, a second insulating film is deposited thereon and holes are formed therein such that the plug electrodes of silicon are exposed. A barrier film is formed on the surfaces of the silicon plugs, and in the holes are formed a dielectric to form lower electrodes of the capacitor elements and an upper electrode therefor.
    Type: Application
    Filed: February 5, 2001
    Publication date: November 8, 2001
    Inventors: Shinpei IIjima, Yoshitaka Nakamura, Masahiko Hiratani, Yuichi Matsui, Naruhiko Nakanishi
  • Publication number: 20010029113
    Abstract: A semiconductor device includes a DRAM having a memory cell constructed by an information storage capacitor C which is comprised of a lower electrode 54 made of a ruthenium film and an upper electrode 62 made of a capacity insulating film 61 and a titanium nitride film and which is connected in series with a memory cell selection MISFET Qs formed on the main surface of a semiconductor substrate 1. The capacity insulating film 61 is made of a multi layered film comprising two layered crystallized tantalum oxide films 56 and 58 each having a film thickness of 10 nm or less. The film thickness of the capacity insulating film 61 is set to 10 to 40 nm.
    Type: Application
    Filed: March 19, 2001
    Publication date: October 11, 2001
    Inventors: Masato Kunitomo, Shinpei Iijima
  • Patent number: 6294420
    Abstract: The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode 18 adjacent an insulating region 26. This base electrode 18 can comprise either polysilicon or a metal. A layer 28 of a first material, such as a siliciding metal, is formed over the base electrode 18 as well as the adjacent insulating region. A self-aligned capacitor electrode 12 can then be formed by reacting the first material 28 with the base electrode 18 and removing unreacted portions of the first material 28 from the insulating region 26. The capacitor is then completed by forming a dielectric layer 16 over the self-aligned capacitor electrode 12 and a second capacitor electrode 14 over the dielectric layer 16.
    Type: Grant
    Filed: January 28, 1998
    Date of Patent: September 25, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Robert Tsu, Isamu Asano, Shinpei Iijima, William R. McKee
  • Patent number: 6235572
    Abstract: A semiconductor device includes a DRAM having a memory cell constructed by an information storage capacitor C which is comprised of a lower electrode 54 made of a ruthenium film and an upper electrode 62 made of a capacity insulating film 61 and a titanium nitride film and which is connected in series with a memory cell selection MISFET Qs formed on the main surface of a semiconductor substrate 1. The capacity insulating film 61 is made of a multi layered film comprising two layered crystallized tantalum oxide films 56 and 58 each having a film thickness of 10 nm or less. The film thickness of the capacity insulating film 61 is set to 10 to 40 nm.
    Type: Grant
    Filed: June 17, 1999
    Date of Patent: May 22, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Masato Kunitomo, Shinpei Iijima
  • Patent number: 6103566
    Abstract: A dynamic random access memory or the like, in which in order to prevent the breakdown voltage deterioration of a capacitive element when a TiN film of an electrode material is deposited by the CVD method over a tantalum film constituting the capacitor insulating film of the capacitive element, a passivation film is formed in advance over the surface of the tantalum oxide film to prevent the tantalum oxide film from contacting a nitrogen-containing reducing gas, when the TiN film is deposited over the tantalum oxide film by the CVD method using a titanium-containing source gas and the nitrogen-containing reducing gas.
    Type: Grant
    Filed: December 9, 1996
    Date of Patent: August 15, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Tsuyoshi Tamaru, Shinpei Iijima, Natsuki Yokoyama, Masayuki Nakata