Abstract: A single-die multi-FBAR (film bulk acoustic resonator) device includes multiple FBARs having different resonant frequencies formed over a single substrate. The FBARs include piezoelectric layers having different thicknesses but with upper electrodes formed at a same height over the substrate, lower electrodes at different heights over the substrate, and different sized air gaps separating the lower electrodes from the substrate.

Abstract: An integrated radio frequency (RF) circuit combines complementary features of passive devices and acoustic filters and includes a first die, a second die, and a third die. The first die includes a substrate having one or more passive devices. The second die includes a first acoustic filter. The second die is stacked and coupled to a first surface of the first die. The third die includes a second acoustic filter. The third die is stacked and coupled to a second surface opposite the first surface of the first die.

Abstract: Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps.

Abstract: An integrated circuit (IC) device includes a die having an integrated passive device (IPD) layer. The integrated circuit device also includes a substrate supporting the die, a molding compound surrounding the die. The integrated circuit device further includes a backside conductive layer on a surface of the die that is distal from the IPD layer. The integrated circuit device also includes vias coupling the backside conductive layer to a ground plane through the molding compound.

Abstract: A capacitor may include a first capacitor plate having a first length. The capacitor may also include an inorganic capacitor dielectric layer on sidewalls and a surface of the first capacitor plate and a second capacitor plate on the inorganic capacitor dielectric layer. The second capacitor plate may have a second length less than the first length of the first capacitor plate. The capacitor may also include a conductive contact landing directly on the first capacitor plate. The conductive contact may land directly on the first capacitor plate by extending through the inorganic capacitor dielectric layer and an organic interlayer dielectric supported by the inorganic capacitor dielectric layer.

Abstract: A microelectromechanical system (MEMS) bond release structure is provided for manufacturing of three-dimensional integrated circuit (3D IC) devices with two or more tiers. The MEMS bond release structure includes a MEMS sacrificial release layer which may have a pillar or post structure, or alternatively, a continuous sacrificial layer for bonding and release.

Abstract: An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.

Abstract: Due to the presence of a glass substrate, it is difficult to fabricate thin conventional passive-on-glass (POG) devices. Also glass dicing has been a throughput bottleneck in fabricating the conventional POG device. To address such disadvantages, devices without the glass substrates are proposed. Support structures may be provided to provide mechanical support. The devices are significantly thinner and allow access to the passive components from both first and second surfaces, which are opposite and exposed surfaces. The proposed POM devices may also be incorporated in a package substrate.

Abstract: A device that includes a single substrate layer, a plurality of interconnects over the single substrate layer, the plurality of interconnects configured to operate as at least one passive component, a first die coupled to the single substrate layer and the plurality of interconnects, and an encapsulation layer that at least partially encapsulates the first die and the plurality of interconnects configured to operate as at least one passive component. In some implementations, the single substrate layer, the first die and the encapsulation layer comprise an overall thickness of about 225 microns (?m) or less. In some implementations, the single substrate layer comprises a thickness of about 75 microns (?m) or less.

Abstract: A single-die multi-FBAR (film bulk acoustic resonator) device includes multiple FBARs having different resonant frequencies formed over a single substrate. The FBARs include piezoelectric layers having different thicknesses but with upper electrodes formed at a same height over the substrate, lower electrodes at different heights over the substrate, and different sized air gaps separating the lower electrodes from the substrate.

Abstract: A passive device may include an inductor having interconnected trace segments. The passive device may also include parallel plate capacitors. Each of the plurality of parallel plate capacitors may have a dielectric layer between a pair of conductive plates. The parallel plate capacitors may not overlap more than one of the interconnected trace segments.

Abstract: A package includes a redistribution portion, a first portion, and a second portion. The first portion is coupled to the redistribution portion. The first portion includes a first switch comprising a plurality of switch interconnects, and a first encapsulation layer that at least partially encapsulates the first switch. The second portion is coupled to the first portion. The second portion includes a first plurality of filters. Each filter includes a plurality of filter interconnects. The second portion also includes a second encapsulation layer that at least partially encapsulates the first plurality of filters. The first portion includes a second switch positioned next to the first switch, where the first encapsulation layer at least partially encapsulates the second switch. The second portion includes a second plurality of filters positioned next to the first plurality of filters, where the second encapsulation layer at least partially encapsulates the second plurality of filters.

Abstract: In a particular aspect, a device includes a substrate including at least one through-substrate via. A metal structure is disposed on a surface of the substrate. The device further includes a semiconductor layer bonded to the substrate. The semiconductor layer includes at least one complimentary metal-oxide-semiconductor (CMOS) transistor and a metal disposed within a second via. The metal is in direct contact with the metal structure.

Abstract: A substrate block is provided that has an increased width. The substrate block comprises two substrate bars, and the substrate bars each comprise a substrate and a plurality of filled vias through the substrate. The substrate block may be used to manufacture package substrates, and these package substrate may be incorporated into a PoP structure. The package substrate includes a carrier having a plurality of vertical interconnections and a bar coupled to the vertical interconnections.

Abstract: In an illustrative example, an apparatus includes a passive-on-glass (POG) device integrated within a glass substrate. The apparatus further includes a semiconductor die integrated within the glass substrate.

Abstract: Disclosed is a heterojunction bipolar transistor, and method of manufacturing the same, including an emitter having a conductive emitter contact coupled to a first side of the emitter, a first side of a base coupled to a second side of the emitter opposite the first side of the emitter, a collector coupled to the base on a second side of the base opposite the emitter, wherein an area of a junction between the base and the collector is less than or equal to an area of a junction between the base and the emitter, a first conductive base contact coupled to the base, and a conductive collector contact coupled to the collector on the side of the collector opposite the emitter and substantially parallel to the first conductive base contact.

Abstract: Methods, devices, systems, and non-transitory processor-readable storage media are disclosed for determining one or more biometric properties of a subject using multiple sensors positioned along a flexible backing. At least one processor of the multi-sensor device may be configured to receive output signals from the multiple sensors, identify at least one output signal from the received output signals that exhibit measurements of a targeted biological structure, determine the one or more biometric properties of the subject based on the identified at least one output signal received from at least one of the multiple sensors, and provide the determined one or more biometric properties.

Abstract: An intergrated circuit (IC) package includes a die, a package substrate coupled to the die, and a first electrostatic discharge (ESD) protection component coupled to the package substrate, where the first electrostatic discharge (ESD) protection component is configured to provide package level electrostatic discharge (ESD) protection. In some implementations, the first electrostatic discharge (ESD) protection component is embedded in the package substrate. In some implementations, the die includes an internal electrostatic discharge (ESD) protection component configured to provide die level electrostatic discharge (ESD) protection. In some implementations, the internal electrostatic discharge (ESD) protection component and the first electrostatic discharge (ESD) protection component are configured to provide cumulative electrostatic discharge (ESD) protection for the die.

Abstract: Examples of monolithic integrated emitter-detector array in a flexible substrate for biometric sensing and associated devices and methods are disclosed. One disclosed example device includes a flexible substrate; a first array of emitters embedded in the flexible substrate, the first array of emitters configured to emit first electromagnetic (EM) signals; a first array of detectors embedded in the flexible substrate, the first array of detectors configured to detect reflections of the first EM signals; a first scanning circuit coupled to the first array of emitters, the first scanning circuit configured to selectively activate individual emitters of the first array of emitters; and a first sensing circuit coupled to individual detectors of the first array of detectors, the first sensing circuit configured to receive a detection signal from at least one of the detectors of the first array of detectors.

Abstract: An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.