Abstract: Some examples of the disclosure may include a package on package integrated package configuration including a first die located above the substrate in a first plane, a second die located above the first die in a second plane with a portion extending past the first die, a third die located above the first die in the second plane with a portion extending past the first die, a fourth die located above the second die and the third die in a third plane with a portion extending past the second die and the third die, and a fifth die located above the second die and the third die in the third plane with a portion extending past the second die and the third die.

Abstract: An integrated circuit device includes a first substrate having a ground plane. The integrated circuit device also includes a second substrate. The second substrate has a first layer of passive devices. The passive devices include at least one inductor on a first side of the second substrate. The first layer of passive devices is substantially orthogonal to the ground plane and the second substrate supported by the first substrate. An inductor magnetic field is substantially parallel to the ground plane.

Abstract: An apparatus includes a first component layer. The component layer includes a first semiconductor device. The apparatus further includes a first hydrophilic layer and a first hydrophobic layer. The first hydrophobic layer is positioned between the first component layer and the first hydrophilic layer. The apparatus further includes a first contact extending through the first hydrophobic layer and the first hydrophilic layer.

Abstract: An integrated circuit (IC) includes a first semiconductor device on a glass substrate. The first semiconductor device includes a first semiconductive region of a bulk silicon wafer. The IC includes a second semiconductor device on the glass substrate. The second semiconductor device includes a second semiconductive region of the bulk silicon wafer. The IC includes a through substrate trench between the first semiconductive region and the second semiconductive region. The through substrate trench includes a portion disposed beyond a surface of the bulk silicon wafer.

Abstract: A capacitor includes a semiconductor substrate. The capacitor also includes a first terminal having a fin disposed on a surface of the semiconductor substrate. The capacitor further includes a dielectric layer disposed onto the fin. The capacitor still further includes a second terminal having a FinFET compatible high-K metal gate disposed proximate and adjacent to the fin.

Abstract: An integrated radio frequency (RF) circuit structure may include a resistive substrate material and a switch. The switch may be arranged in a silicon on insulator (SOI) layer supported by the resistive substrate material. The integrated RF circuit structure may also include an isolation layer coupled to the SOI layer. The integrated RF circuit structure may further include a filter, composed of inductors and capacitors. The filter may be arranged on a surface of the integrated RF circuit structure, opposite the resistive substrate material. In addition, the switch may be arranged on a first surface of the isolation layer.

Abstract: Some features pertain to an integrated device that includes a die and a first redistribution portion coupled to the die. The first redistribution portion includes at least one dielectric layer and a capacitor. The capacitor includes a first plate, a second plate, and an insulation layer located between the first plate and the second plate. The first redistribution portion further includes several first pins coupled to the first plate of the capacitor. The first redistribution portion further includes several second pins coupled to the second plate of the capacitor. In some implementations, the capacitor includes the first pins and/or the second pins. In some implementations, at least one pin from the several first pins traverses through the second plate to couple to the first plate of the capacitor. In some implementations, the second plate comprises a fin design.

Abstract: Some features pertain to an integrated device that include a first integrated circuit (IC) package comprising a first laminated substrate, a flexible connector coupled to the first laminated substrate, and a second integrated circuit (IC) package comprising a second laminated substrate. The second laminated substrate is coupled to the flexible connector. The flexible connector includes a dielectric layer and an interconnect. The dielectric layer and the interconnect substantially extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer and the interconnect of the flexible connector, contiguously extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer extends into a substantial portion of the first laminated substrate. In some implementations, the dielectric layer includes polyimide (PI) layer.

Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.

Abstract: An integrated circuit (IC) includes a first semiconductor device on a glass substrate. The first semiconductor device includes a first semiconductive region of a bulk silicon wafer. The IC includes a second semiconductor device on the glass substrate. The second semiconductor device includes a second semiconductive region of the bulk silicon wafer. The IC includes a through substrate trench between the first semiconductive region and the second semiconductive region. The through substrate trench includes a portion disposed beyond a surface of the bulk silicon wafer.

Abstract: Some novel features pertain to an integrated device package that includes an encapsulation portion and a redistribution portion. The encapsulation portion includes a first die, a first set of vias coupled to the first die, a second die, a second set of vias coupled to the second die, a bridge, and an encapsulation layer. The bridge is configured to provide an electrical path between the first die and the second die. The bridge is coupled to the first die through the first set of vias. The bridge is further coupled to the second die through the second set of vias. The encapsulation layer at least partially encapsulates the first die, the second die, the bridge, the first set of vias, and the second set of vias. The redistribution portion is coupled to the encapsulation portion. The redistribution portion includes a set of redistribution interconnects, and at least one dielectric layer.

Abstract: A substrate includes a plurality of vias that are lined with dielectric polymer having a substantially uniform thickness. This substantial uniform thickness provides a lumen within each dielectric-polymer-layer-lined via that is substantially centered within the via. Subsequent deposition of metal into the lumen for each dielectric-polymer-layer-lined via thus provides conductive vias having substantially centered metal conductors.

Abstract: An integrated circuit (IC) package includes a die, a package substrate coupled to the die, and a first electrostatic discharge (ESD) protection component coupled to the package substrate, where the first electrostatic discharge (ESD) protection component is configured to provide package level electrostatic discharge (ESD) protection. In some implementations, the first electrostatic discharge (ESD) protection component is embedded in the package substrate. In some implementations, the die includes an internal electrostatic discharge (ESD) protection component configured to provide die level electrostatic discharge (ESD) protection. In some implementations, the internal electrostatic discharge (ESD) protection component and the first electrostatic discharge (ESD) protection component are configured to provide cumulative electrostatic discharge (ESD) protection for the die.

Abstract: Some features pertain to an integrated device that includes a dielectric layer configured as a base for the integrated device, several redistribution metal layers in the dielectric layer, a first wafer level die coupled to a first surface of the dielectric layer, and a second wafer level die coupled to the first wafer level die. The dielectric layer includes several dielectric layers. In some implementations, the first wafer level die is coupled to the redistribution metal layers through a first set of interconnects. In some implementations, the first wafer level die includes several through substrate vias (TSVs). In some implementations, the second wafer level die is coupled to the redistribution metal layers through a first set of interconnects, the TSVs, a second set of interconnects, and a set of solder balls. In some implementations, the integrated device includes an encapsulation layer that encapsulates the first and second wafer level dies.

Abstract: Some features pertain to an integrated device that includes a substrate, several metal layers coupled to the substrate, several dielectric layers coupled to the substrate, and a redistribution portion coupled to one of the metal layers. The redistribution portion includes a first metal redistribution layer, an insulation layer coupled to the first metal redistribution layer, and a second metal redistribution layer coupled to the insulation layer. The first metal redistribution layer, the insulation layer, and the second metal redistribution layer are configured to operate as a capacitor in the integrated device. In some implementations, the capacitor is a metal-insulator-metal (MIM) capacitor.

Abstract: Copper (Cu) grain boundaries can move during a thermal cycle resulting in the Cu grain position being offset. Such Cu pumping can disturb the surface of a bottom metal, and can physically break a dielectric of a metal-insulator-metal (MIM) capacitor. By capping the bottom metal with an anchoring cap, Cu pumping is reduced or eliminated.

Abstract: Some implementations provide a semiconductor device that includes a first die and an optical receiver. The first die includes a back side layer having a thickness that is sufficiently thin to allow an optical signal to traverse through the back side layer. The optical receiver is configured to receive several optical signals through the back side layer of the first die. In some implementations, each optical signal originates from a corresponding optical emitter coupled to a second die. In some implementations, the back side layer is a die substrate. In some implementations, the optical signal traverses a substrate portion of the back side layer. The first die further includes an active layer. The optical receiver is part of the active layer. In some implementations, the semiconductor device includes a second die that includes an optical emitter. The second die coupled to the back side of the first die.

Abstract: Some novel features pertain to an integrated device that includes an encapsulation layer, a via structure traversing the encapsulation layer, and a pad. The via structure includes a via that includes a first side, a second side, and a third side. The via structure also includes a barrier layer surrounding at least the first side and the third side of the via. The pad is directly coupled to the barrier layer of the via structure. In some implementations, the integrated device includes a first dielectric layer coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a substrate coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a first die coupled to the substrate, where the encapsulation layer encapsulates the first die. In some implementations, the via includes a portion configured to operate as a pad.

Abstract: Some examples of the disclosure may include a package on package integrated package configuration including a first die located above the substrate in a first plane, a second die located above the first die in a second plane with a portion extending past the first die, a third die located above the first die in the second plane with a portion extending past the first die, a fourth die located above the second die and the third die in a third plane with a portion extending past the second die and the third die, and a fifth die located above the second die and the third die in the third plane with a portion extending past the second die and the third die.

Abstract: Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps.