Patents by Inventor Shiro Tsunai

Shiro Tsunai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7940322
    Abstract: A focus detecting device includes a focus detecting optical system which forms a plurality of object images. A photoelectric conversion element array includes a plurality of pixels and subjects each of the plural object images formed by the focus detecting optical system to photoelectric conversion. An electric charge transfer path transfers an electric charge obtained by the photoelectric conversion subjected by the photoelectric conversion element array. A focus detecting section performs focus detection with respect to a plurality of focus areas on the basis of a signal associated with an electric charge transferred by the electric charge transfer path. A plurality of effective pixel regions corresponding to the plural focus areas are arranged in the arrangement direction of the pixels of the photoelectric conversion element array, and ineffective pixel regions are arranged between the plural effective pixel regions.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: May 10, 2011
    Assignee: Olympus Imaging Corporation
    Inventors: Tetsuo Kikuchi, Kosei Tamiya, Shiro Tsunai
  • Patent number: 7485837
    Abstract: In an autofocus image sensor, monitoring pixels are disposed adjacent to a pixel array over a length equal to that of the pixel array in each of a standard portion and a reference portion. Signals from the monitoring pixels of both of the standard portion and the reference portion are subjected to arithmetic operation to control accumulation of electric charges. Thus, an error in position detection is minimized.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: February 3, 2009
    Assignees: NEC Electronics Corporation, Olympus Corporation, Olympus Imaging Corp.
    Inventors: Shiro Tsunai, Kosei Tamiya, Tetsuo Kikuchi
  • Publication number: 20080225152
    Abstract: The signal charge corresponding to the amount of light is obtained from a photodiode section and is then stored in a charge storage section under the control of a first control gate. An additional charge storage section may be provided between the photodiode section and the charge storage section. The signal charge thus stored in the charge storage section is supplied to a charge transfer section under the control of a second control gate.
    Type: Application
    Filed: February 4, 2008
    Publication date: September 18, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Shiro TSUNAI
  • Publication number: 20080212955
    Abstract: A focus detecting device includes a focus detecting optical system which forms a plurality of object images. A photoelectric conversion element array includes a plurality of pixels and subjects each of the plural object images formed by the focus detecting optical system to photoelectric conversion. An electric charge transfer path transfers an electric charge obtained by the photoelectric conversion subjected by the photoelectric conversion element array. A focus detecting section performs focus detection with respect to a plurality of focus areas on the basis of a signal associated with an electric charge transferred by the electric charge transfer path. A plurality of effective pixel regions corresponding to the plural focus areas are arranged in the arrangement direction of the pixels of the photoelectric conversion element array, and ineffective pixel regions are arranged between the plural effective pixel regions.
    Type: Application
    Filed: February 21, 2008
    Publication date: September 4, 2008
    Applicants: Olympus Imaging Corp., Olympus Corporation, NEC Electronics Corporation
    Inventors: Tetsuo Kikuchi, Kosei Tamiya, Shiro Tsunai
  • Publication number: 20080128590
    Abstract: In an autofocus image sensor, monitoring pixels are disposed adjacent to a pixel array over a length equal to that of the pixel array in each of a standard portion and a reference portion. Signals from the monitoring pixels of both of the standard portion and the reference portion are subjected to arithmetic operation to control accumulation of electric charges. Thus, an error in position detection is minimized.
    Type: Application
    Filed: October 26, 2007
    Publication date: June 5, 2008
    Applicants: NEC ELECTRONICS CORPORATION, OLYMPUS CORPORATION, OLYMPUS IMAGING CORP.
    Inventors: Shiro TSUNAI, Kosei TAMIYA, Tetsuo KIKUCHI
  • Patent number: 7196303
    Abstract: A CCD image sensor includes a first diode row comprised of photodiodes arranged in a row, a second diode row extending in parallel with the first diode row and comprised of photodiodes arranged in a row, photodiodes in the second diode row being staggered by a half pitch relative to photodiodes in the first diode row, a first charge transfer device transferring signal charges received from K-th photodiodes in the first diode row wherein K is an odd number, a second charge transfer device transferring signal charges received from L-th photodiodes in the first diode row wherein L is an even number, a third charge transfer device transferring signal charges received from K-th photodiodes in the second diode row, a fourth charge transfer device transferring signal charges received from L-th photodiodes in the second diode row, a charge-detecting capacitor receiving signal charges at different timings from one another from the first to fourth charge transfer devices, and a charge-detector detecting signal charges
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: March 27, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Shiro Tsunai
  • Publication number: 20070045669
    Abstract: An image sensor according to an embodiment of the invention includes: a plurality of pixels arranged in line; a reading gate adjacent to the plurality of pixels; a plurality of memory gates formed adjacent to the reading gate and corresponding to the plurality of pixels; a plurality of memory control gates corresponding to the memory gates; and a CCD accumulation gate common to the plurality of memory control gates.
    Type: Application
    Filed: July 18, 2006
    Publication date: March 1, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Shiro Tsunai
  • Patent number: 7002413
    Abstract: A voltage amplification circuit is provided which is capable of faithfully amplifying an input signal even in an inverting amplifier placed in a second stage being DC-coupled to an inverting amplifier placed in a first stage. By DC-coupling the inverting amplifiers and by setting an amplifying operation starting input voltage in the inverting amplifier placed in the first stage to be lower than that in the inverting amplifier placed in the second stage, the voltage amplification circuit that can provide a large amplification factor is realized.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: February 21, 2006
    Assignee: NEC Electronics Corporation
    Inventor: Shiro Tsunai
  • Patent number: 6784742
    Abstract: A voltage amplifying circuit (100) that may have a selectable gain has been disclosed. Voltage amplifying circuit (100) may include a voltage amplifier (2) and a gain changing unit (7). A gain changing unit (2) may be capable of changing at least one of: a capacitance between a signal input terminal (6) and an input terminal of a voltage amplifier, the capacitance between an input terminal of a voltage amplifier and a ground (or reference potential), and a capacitance between an input and an output terminal (3) of a voltage amplifier. In this way, a gain from a signal input terminal (6) to an output terminal (3) of a voltage amplifier of a voltage amplifying circuit (100) may be changed.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: August 31, 2004
    Assignee: NEC Electronics Corporation
    Inventors: Shiro Tsunai, Akira Uemura
  • Publication number: 20040109075
    Abstract: A CCD image sensor includes a first diode row comprised of photodiodes arranged in a row, a second diode row extending in parallel with the first diode row and comprised of photodiodes arranged in a row, photodiodes in the second diode row being staggered by a half pitch relative to photodiodes in the first diode row, a first charge transfer device transferring signal charges received from K-th photodiodes in the first diode row wherein K is an odd number, a second charge transfer device transferring signal charges received from L-th photodiodes in the first diode row wherein L is an even number, a third charge transfer device transferring signal charges received from K-th photodiodes in the second diode row, a fourth charge transfer device transferring signal charges received from L-th photodiodes in the second diode row, a charge-detecting capacitor receiving signal charges at different timings from one another from the first to fourth charge transfer devices, and a charge-detector detecting signal charges
    Type: Application
    Filed: December 1, 2003
    Publication date: June 10, 2004
    Applicant: NEC Electronics Corporation
    Inventor: Shiro Tsunai
  • Publication number: 20040104776
    Abstract: A voltage amplification circuit is provided which is capable of faithfully amplifying an input signal even in an inverting amplifier placed in a second stage being DC-coupled to an inverting amplifier placed in a first stage. By DC-coupling the inverting amplifiers and by setting an amplifying operation starting input voltage in the inverting amplifier placed in the first stage to be lower than that in the inverting amplifier placed in the second stage, the voltage amplification circuit that can provide a large amplification factor is realized.
    Type: Application
    Filed: October 22, 2003
    Publication date: June 3, 2004
    Applicant: NEC Electronics Corporation
    Inventor: Shiro Tsunai
  • Patent number: 6720593
    Abstract: A charge-coupled device (CCD) includes first-level transfer electrodes and second-level transfer electrodes alternately arranged along a transfer channel, wherein charge storage sections underlying the first-level transfer electrodes have a larger width than barrier sections underlying the second-level transfer electrodes. First and second interconnect lines supply two-phase driving signals to the transfer electrodes. Contact plugs connecting the first interconnect line to the transfer electrodes and contact plugs connecting the second interconnect line are located at opposite sides with respect to the center line of the transfer channel.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: April 13, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Shiro Tsunai
  • Publication number: 20030213983
    Abstract: A charge-coupled device (CCD) includes first-level transfer electrodes and second-level transfer electrodes alternately arranged along a transfer channel, wherein charge storage sections underlying the first-level transfer electrodes have a larger width than barrier sections underlying the second-level transfer electrodes. First and second interconnect lines supply two-phase driving signals to the transfer electrodes. Contact plugs connecting the first interconnect line to the transfer electrodes and contact plugs connecting the second interconnect line are located at opposite sides with respect to the center line of the transfer channel.
    Type: Application
    Filed: May 6, 2003
    Publication date: November 20, 2003
    Applicant: NEC Electronics Corporation
    Inventor: Shiro Tsunai
  • Publication number: 20030210435
    Abstract: A color image sensor includes a plurality of image elements, a plurality of read gate sections, a plurality of vertical scanning charge transfer sections, and a plurality of transfer switch sections. The plurality of image elements are arranged in a matrix of rows and columns and each of the plurality of image elements generates an electric charge in response to incidence of light. The plurality of read gate sections are provided for the plurality of image elements, and each of the plurality of image elements controls transfer of the electric charge generated in a corresponding one of the plurality of image elements. Each of the plurality of vertical scanning charge transfer sections is provided for every column of the matrix to hold and transfer the electric charges transferred from a corresponding column of the plurality of read gate sections.
    Type: Application
    Filed: May 2, 2003
    Publication date: November 13, 2003
    Applicant: NEC Electronics Corporation
    Inventor: Shiro Tsunai
  • Patent number: 6618088
    Abstract: A charge transfer device is disclosed wherein three pixel rows are arranged adjacently to each other. First to third pixel rows are arranged adjacently to each other, and the charge transfer device includes a first charge transfer element for reading out and transferring signal charges generated in the first pixel row and a second charge transfer element for reading out and transferring signal charges generated in the second and third pixel rows. Second readout electrodes for reading out signal charges generated in the second pixel row into the second charge transfer element are provided with one electrode placed between adjacent pixels of the third pixel row.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: September 9, 2003
    Assignee: NEC Electronics Corporation
    Inventors: Shiro Tsunai, Kazuo Miwada
  • Patent number: 6603144
    Abstract: P-type ion implantation is done in N well 15, so as to form a charge drain control layer 17 and form a photodiode N well 16 and OFD drain 5, the result being that, even if there is variation in the potential of the photodiode N well 16 making up the photodiode, because the variation in the potential of the charge drain control layer 17 is in the same direction as the potential of the photodiode N well 16, so that variation does not occur in the maximum amount of electrical charge that can be accumulated, the result being that there is no variation in the signal in the saturation condition.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: August 5, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Shiro Tsunai
  • Publication number: 20030025950
    Abstract: A sensor chip arranged in a casing having a window portion on the side thereof to be faced to a medium to be read takes in the form of a single long chip. In particular, a single long and seamless sensor chip having a plurality of photoelectric conversion elements arranged thereon throughout a length of the window portion of the casing is mounted on a long supporting substrate having a length long enough to support the whole sensor chip. The sensor chip and the supporting substrate are bonded together such that transmission of stress due to external force exerted on the supporting substrate to the sensor chip is restricted.
    Type: Application
    Filed: July 17, 2002
    Publication date: February 6, 2003
    Applicant: NEC CORPORATION
    Inventor: Shiro Tsunai
  • Patent number: 6515318
    Abstract: A charge transfer device is provided which is capable of reducing a reset field-through noise in a stable manner without being affected by characteristics of transistors and without occurrence of a mustache-shaped pulse-like noise. The charge transfer device is made up of a floating diffusion region used to convert a signal charge transferred from a CCD (Charge Coupled Device) into a voltage, resetting unit used to eject the signal charge accumulated in the floating diffusion region in response to a reset pulse, a first stage source follower used to current-amplify the voltage and second stage source follower in which load is changed in response to the reset pulse and which is used to current-amplify an output voltage of the first stage source follower.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: February 4, 2003
    Assignee: NEC Corporation
    Inventor: Shiro Tsunai
  • Publication number: 20030006843
    Abstract: A voltage amplifying circuit (100) that may have a selectable gain has been disclosed. Voltage amplifying circuit (100) may include a voltage amplifier (2) and a gain changing unit (7). A gain changing unit (2) may be capable of changing at least one of: a capacitance between a signal input terminal (6) and an input terminal of a voltage amplifier, the capacitance between an input terminal of a voltage amplifier and a ground (or reference potential), and a capacitance between an input and an output terminal (3) of a voltage amplifier. In this way, a gain from a signal input terminal (6) to an output terminal (3) of a voltage amplifier of a voltage amplifying circuit (100) may be changed.
    Type: Application
    Filed: July 3, 2002
    Publication date: January 9, 2003
    Inventors: Shiro Tsunai, Akira Uemura
  • Publication number: 20020093059
    Abstract: In a protective circuit, on a semiconductor substrate of a first conduction type an island-shaped first well of a second conduction type for formation of a protective element for bypassing the above-noted static electricity and a second well of the second conduction type biased to a prescribed potential and intended for formation of a circuit element of the internal circuit are formed so as to be mutually separated, the first well and the second well being connected via a resistance. By this configuration, when static electricity is applied the potential of the first well changes in response thereto, and a current flowing from the first well into the second well is appropriately suppressed, thereby preventing destruction of the internal circuit by the static electricity.
    Type: Application
    Filed: January 11, 2002
    Publication date: July 18, 2002
    Applicant: NEC CORPORATION
    Inventor: Shiro Tsunai