Abstract: Metal contact openings are etched in the barrier layer of a group III-N HEMT with a first gas combination that etches down into the barrier layer, and a second gas combination that etches further down into the barrier layer to a depth that lies above the top surface of a channel layer that touches and lies below the barrier layer.

Abstract: Metal contacts with low contact resistances are formed in a group III-N HEMT by forming metal contact openings in the barrier layer of the group III-N HEMT to have depths that correspond to low contact resistances. The metal contact openings are etched in the barrier layer with a first gas combination that etches down into the barrier layer, and a second gas combination that etches further down into the barrier layer.

Abstract: A hydrostatic guide system including a guide table, a transfer table, a floating amount sensor attached to the transfer table, and a control unit. The transfer table has an inner portion, in which a magnetic attraction unit including a yoke and an electromagnet is embedded, and an outer shell portion, which covers the side surface and the upper surface of the inner portion. After the inner portion houses the yoke and the electromagnet, a gap around the yoke and the electromagnet is filled with a material having appropriate strength, so that the inner portion is integrated with the outer shell portion, and the transfer surface is flattened as whole. A surrounding groove is provided around the transfer table, and pressurized fluid supplied into the groove is jetted out to the guide table.

Abstract: A dynamic random access memory device having a number of sense amplifier banks (404a-404h) is disclosed. Each sense amplifier bank (404a-404h) has an associated memory array (402a-402h) and supply switch (406a-406h). In a given sense operation, data signals are coupled from a memory array (402a-402h) to its associated sense amplifier bank (404a-404h). Selection of the memory array (402a-402h) is determined by address signals (MS0-MS7). The supply switches (406a-406h) provide a sense amplifier supply voltage at a supply node (708) of its associated sense amplifier bank (404a-404h). At the initial portion of a sense operation, the supply switch (406a-406h) couples the high power supply voltage (VDD) to its associated supply node (708). After a predetermined time period, the supply switch couples a reduced array voltage (VDL) to its associated supply node (708). The switching operation is determined by an overdrive signal (SAOV).

Abstract: A semiconductor memory is provided with a main amplifier circuit that is capable of selectively driving and precharging two I/O buses in conjunction with a write amplifier. The main amplifier circuit includes a separation and precharge section and an activation section. The activation section drives a signal for activating the first section to precharge the two I/O signals only when the two I/O buses are not being separated. The main amplifier circuit also includes both a main output bus and a test output bus. In so doing, the semiconductor memory can operate in a normal mode and a test mode. In the test mode, twice as many memory cells of the semiconductor memory can be accessed simultaneously, thereby reducing test time. The semiconductor memory, which can be one of many different data widths, has different sized output buses associated with each data width. Output buses with a relatively large capacitance can be produced with a large width, giving them a relatively small resistance.

Abstract: A circuit for testing a memory cell array 100. The circuit includes a test circuit 104 coupled to the array and includes a data output line 106 and a failure signal output line 108. A shift register 110, which includes a plurality of latches, a clock signal input 114, and an output line 116, is connected to the failure signal output line of the test circuit. The circuit also includes a three-state output buffer driver 118, the buffer driver including a data input line, a failure signal input line, and a data output line. The failure signal line of the buffer driver is connected to the output line of the shift register 110. Upon detecting a defective memory cell in the array, the test circuit produces a failure signal on the failure signal output line 116 of the test circuit. The failure signal is then sent to the shift register 110 causing the buffer driver 118 to enter a high-impedance state in response to said failure signal.

Abstract: A memory circuit includes a bond option circuit 106 having an input and an output, and row control circuitry 100 coupled to the output of the bond option circuit, the row control circuitry including address terminals, A12 and A13. The memory circuit also includes column control circuitry 102 coupled to the output of the bond option circuit, the column control circuitry 102 also including address terminals, A12 and A13. A memory cell array is coupled to the row control and column control circuitry and is arranged in a first plurality of banks of memory cells, the banks being selectable by a combination of address signals on the address terminals of the row control and column control circuitry. In response to a first signal at the input of the bond option circuit 106, the bond option circuit produces a second signal at the output of the bond option circuit that is coupled to the row control 100 and column control 102 circuitry.

Abstract: A defect remedy LSI mounted on a memory module, comprising: an input interface portion for capturing address and control signals, the input interface portion being the same as that of a dynamic RAM; an input/output interface portion corresponding to a data bus of a memory device comprised of a plurality of dynamic random access memories; a memory circuit to which a chip address and an X defective address of any of the plurality of random access memories are electrically written, the memory circuit being substantially made nonvolatile; a redundancy remedy RAM portion composed of a static RAM wherein a word line is selected by a compare match signal between an X address signal and the defective address of the memory circuit, the X address signal and the defective address being captured via the input interface portion, and a column is selected by a Y address signal captured via the input interface portion; a selecting portion for connecting a data input/output bus of the redundancy remedy RAM portion to an input

Abstract: A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.

Abstract: A non-inverting buffer circuit device suited for an input buffer circuit of a semiconductor memory is provided so that the number of logic gate stages can be reduced to realize a high speed operation. The circuit is designed in such a way that an MOS transistor at an input stage drives a bipolar transistor at an output stage to produce an output. An n-channel MOS transistor and a p-channel MOS transistor connected in parallel between the base and the collector of the bipolar transistor are on/off controlled by an inverted signal of the input digital signal and a non-inverted signal thereof, respectively. In another aspect, the input buffer circuit includes an inverted signal outputting circuit, and a non-inverted signal outputting circuit in the set mode the input signal in the non-inverted state and outputting in the reset mode the signal at the prescribed potential.

Abstract: A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.

Abstract: A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as curent signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.

Abstract: A simple and efficient method of manufacturing a syringe needle is provided herein, which involves spreading a resin solution on the entire inside and outside of a cut stainless steel tube having the dimensions of a syringe needle, hardening the resin on the inside and outside of said cut tube, removing the hardened resin from the outside of the cut tube, grinding one end of the tube with a grinder to form a main bevel, changing the contact angle between the grinder and the cut tube to form side bevels to produce a syringe needle tube having a piercing point at the ground edge of said tube, and washing away grinding materials and pollutants from the tube.

Abstract: An automatic grinder for grinding a syringe needle point includes a holder for holding a tube to be ground, a grinder, a hold-angle changer to change the angle at which the tube is held, a device to change the angular alignment of the tube by rotating the tube about its axis, a grinding volume changer to change the spacing between the holder and the grinder, a reciprocator to reciprocate the tube holder relative to the grinder for carrying out a grinding operation, a space adjuster to compensate for wear of the grinding surface in the grinder, and a grinding controller for automatic coordination of these units according to a preset program.