Patents by Inventor Shu-Hsiao TSAI
Shu-Hsiao TSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967613Abstract: A semiconductor structure includes a substrate, and an active device and a passive device over the substrate. The active device is disposed in a first region of the substrate, and the passive device is disposed in a second region of the substrate. The semiconductor structure further includes a shielding structure and a passivation layer. The shielding structure includes a barrier layer and a ceiling layer. The barrier layer is on the passive device and the active device, and the ceiling layer is on the barrier layer. The passivation layer is under the barrier layer and covers a top surface of the passive device. An air cavity is defined by sidewalls of the barrier layer, a bottom surface of the ceiling layer, and the substrate.Type: GrantFiled: May 16, 2023Date of Patent: April 23, 2024Assignee: WIN SEMICONDUCTORS CORP.Inventors: Ju-Hsien Lin, Jung-Tao Chung, Shu-Hsiao Tsai, Hsi-Tsung Lin, Chen-An Hsieh, Yi-Han Chen, Yao-Ting Shao
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Patent number: 11791404Abstract: A bipolar transistor includes a substrate, a sub-collector layer, a collector layer, a base layer, an emitter layer, a passivation layer, and a collector electrode. The sub-collector layer is formed over the substrate. The collector layer is formed over the sub-collector layer. The base layer is formed over the collector layer. The emitter layer is formed over the base layer. The passivation layer is formed over the substrate and covering a sidewall of the collector layer. The collector electrode is connected to the sub-collector layer through an opening in the passivation layer. The opening exposes at least a portion of the sub-collector layer.Type: GrantFiled: September 29, 2021Date of Patent: October 17, 2023Assignee: WIN SEMICONDUCTORS CORP.Inventors: Chien-Rong Yu, Shu-Hsiao Tsai, Jui-Pin Chiu
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Publication number: 20230317633Abstract: A semiconductor chip includes an active device and a passive device formed over a substrate. A passivation layer covers the active device and the passive device. A barrier structure surrounds the active device. A ceiling layer is formed across the barrier structure over the active device. The ceiling layer has an opening exposing the barrier structure.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Inventors: Chang-Hwang HUA, Chun-Han SONG, Rong-Hao SYU, Hsi-Tsung LIN, Shu-Hsiao TSAI
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Publication number: 20230282697Abstract: A semiconductor structure includes a substrate, and an active device and a passive device over the substrate. The active device is disposed in a first region of the substrate, and the passive device is disposed in a second region of the substrate. The semiconductor structure further includes a shielding structure and a passivation layer. The shielding structure includes a barrier layer and a ceiling layer. The barrier layer is on the passive device and the active device, and the ceiling layer is on the barrier layer. The passivation layer is under the barrier layer and covers a top surface of the passive device. An air cavity is defined by sidewalls of the barrier layer, a bottom surface of the ceiling layer, and the substrate.Type: ApplicationFiled: May 16, 2023Publication date: September 7, 2023Inventors: Ju-Hsien LIN, Jung-Tao CHUNG, Shu-Hsiao TSAI, Hsi-Tsung LIN, Chen-An HSIEH, Yi-Han CHEN, Yao-Ting SHAO
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Patent number: 11695037Abstract: A semiconductor structure includes a substrate, a passive device and an active device over the substrate. The active device is formed in the first region of the substrate, and the passive device is formed in the second region of the substrate. The semiconductor structure further includes a passivation layer that covers the top surface of the passive device. The passivation layer has an opening that exposes the active device.Type: GrantFiled: January 12, 2021Date of Patent: July 4, 2023Assignee: WIN SEMICONDUCTORS CORP.Inventors: Ju-Hsien Lin, Jung-Tao Chung, Shu-Hsiao Tsai, Hsi-Tsung Lin, Chen-An Hsieh, Yi-Han Chen, Yao-Ting Shao
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Publication number: 20230126870Abstract: A transistor device includes a substrate and a gate structure. The gate structure is disposed on the substrate. The gate structure includes a first metal layer and a refractory metal layer disposed on the first metal layer, wherein the first metal layer is disconnected and the refractory metal layer is disconnected.Type: ApplicationFiled: October 17, 2022Publication date: April 27, 2023Inventors: Chang-Hwang HUA, Shu-Hsiao TSAI, Rong-Hao SYU, Chun-Han SONG, Pei-Ying WU, Zong-Zheng YAN
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Patent number: 11575030Abstract: A heterojunction bipolar transistor includes an emitter layer on a base layer on a collector layer on an upper sub-collector layer over a bottom sub-collector layer, a first dielectric film over the bottom sub-collector layer, the base layer and the emitter layer, a base electrode on the first dielectric film, electrically connected to the base layer through at least one first via hole in the first dielectric film, a second dielectric film on the first dielectric film and the base electrode, and a conductive layer on the second dielectric film, with conductive layer electrically connected to base electrode through a second via hole disposed in the second dielectric film, first dielectric film between the base electrode and first sidewall of a stack including the base layer and the collector layer, and second via hole laterally separated from the base layer.Type: GrantFiled: October 14, 2021Date of Patent: February 7, 2023Assignee: WIN SEMICONDUCTORS CORP.Inventors: She-Hsin Hsiao, Rong-Hao Syu, Shu-Hsiao Tsai
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Patent number: 11411080Abstract: A heterojunction bipolar transistor includes a bottom sub-collector layer formed over a substrate. The heterojunction bipolar transistor also includes an upper sub-collector layer formed over the bottom sub-collector layer. The heterojunction bipolar transistor also includes a collector layer formed over the upper sub-collector layer. The heterojunction bipolar transistor also includes a base layer formed over the collector layer. The heterojunction bipolar transistor also includes an emitter layer formed over the base layer. The heterojunction bipolar transistor also includes a passivation layer covering the bottom sub-collector layer, the upper sub-collector layer, the collector layer, the base layer, and the emitter layer. The heterojunction bipolar transistor also includes a collector electrode that covers the portion of the passivation layer that is over the sidewall of the upper sub-collector layer.Type: GrantFiled: January 5, 2021Date of Patent: August 9, 2022Assignee: WIN SEMICONDUCTORS CORP.Inventors: Chien-Rong Yu, Shu-Hsiao Tsai, Jui-Pin Chiu, She-Hsin Hsiao
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Publication number: 20220223685Abstract: A semiconductor structure includes a substrate, a passive device and an active device over the substrate. The active device is formed in the first region of the substrate, and the passive device is formed in the second region of the substrate. The semiconductor structure further includes a passivation layer that covers the top surface of the passive device. The passivation layer has an opening that exposes the active device.Type: ApplicationFiled: January 12, 2021Publication date: July 14, 2022Inventors: Ju-Hsien LIN, Jung-Tao CHUNG, Shu-Hsiao TSAI, Hsi-Tsung LIN, Chen-An HSIEH, Yi-Han CHEN, Yao-Ting SHAO
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Publication number: 20220216303Abstract: A heterojunction bipolar transistor includes a bottom sub-collector layer formed over a substrate. The heterojunction bipolar transistor also includes an upper sub-collector layer formed over the bottom sub-collector layer. The heterojunction bipolar transistor also includes a collector layer formed over the upper sub-collector layer. The heterojunction bipolar transistor also includes a base layer formed over the collector layer. The heterojunction bipolar transistor also includes an emitter layer formed over the base layer. The heterojunction bipolar transistor also includes a passivation layer covering the bottom sub-collector layer, the upper sub-collector layer, the collector layer, the base layer, and the emitter layer. The heterojunction bipolar transistor also includes a collector electrode that covers the portion of the passivation layer that is over the sidewall of the upper sub-collector layer.Type: ApplicationFiled: January 5, 2021Publication date: July 7, 2022Inventors: Chien-Rong YU, Shu-Hsiao TSAI, Jui-Pin CHIU, She-Hsin HSIAO
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Publication number: 20220052188Abstract: A heterojunction bipolar transistor includes an emitter layer on a base layer on a collector layer on an upper sub-collector layer over a bottom sub-collector layer, a first dielectric film over the bottom sub-collector layer, the base layer and the emitter layer, a base electrode on the first dielectric film, electrically connected to the base layer through at least one first via hole in the first dielectric film, a second dielectric film on the first dielectric film and the base electrode, and a conductive layer on the second dielectric film, with conductive layer electrically connected to base electrode through a second via hole disposed in the second dielectric film, first dielectric film between the base electrode and first sidewall of a stack including the base layer and the collector layer, and second via hole laterally separated from the base layer.Type: ApplicationFiled: October 14, 2021Publication date: February 17, 2022Inventors: She-Hsin Hsiao, Rong-Hao Syu, Shu-Hsiao Tsai
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Publication number: 20220020868Abstract: A bipolar transistor includes a substrate, a sub-collector layer, a collector layer, a base layer, an emitter layer, a passivation layer, and a collector electrode. The sub-collector layer is formed over the substrate. The collector layer is formed over the sub-collector layer. The base layer is formed over the collector layer. The emitter layer is formed over the base layer. The passivation layer is formed over the substrate and covering a sidewall of the collector layer. The collector electrode is connected to the sub-collector layer through an opening in the passivation layer. The opening exposes at least a portion of the sub-collector layer.Type: ApplicationFiled: September 29, 2021Publication date: January 20, 2022Inventors: Chien-Rong YU, Shu-Hsiao TSAI, Jui-Pin CHIU
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Patent number: 11177374Abstract: A heterojunction bipolar transistor includes an emitter layer on a base layer on a collector layer on an upper sub-collector layer over a bottom sub-collector layer, a first dielectric film over the bottom sub-collector layer, the base layer and the emitter layer, a base electrode on the first dielectric film, electrically connected to the base layer through at least one first via hole in the first dielectric film, a second dielectric film on the first dielectric film and the base electrode, and a conductive layer on the second dielectric film, with conductive layer electrically connected to base electrode through a second via hole disposed in the second dielectric film, first dielectric film between the base electrode and first sidewall of a stack including the base layer and the collector layer, and second via hole laterally separated from the base layer.Type: GrantFiled: August 11, 2020Date of Patent: November 16, 2021Assignee: WIN SEMICONDUCTORS CORP.Inventors: She-Hsin Hsiao, Rong-Hao Syu, Shu-Hsiao Tsai
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Patent number: 11164962Abstract: A bipolar transistor includes an upper sub-collector layer, a collector layer, a base layer, an emitter layer, and a collector electrode. The collector layer is disposed on the upper sub-collector layer. The base layer is disposed on the collector layer. An emitter layer is disposed on the base layer. The collector electrode is disposed directly on a sidewall of the upper sub-collector layer.Type: GrantFiled: January 6, 2020Date of Patent: November 2, 2021Assignee: WIN SEMICONDUCTORS CORP.Inventors: Chien-Rong Yu, Shu-Hsiao Tsai, Jui-Pin Chiu
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Publication number: 20210210626Abstract: A bipolar transistor includes an upper sub-collector layer, a collector layer, a base layer, an emitter layer, and a collector electrode. The collector layer is disposed on the upper sub-collector layer. The base layer is disposed on the collector layer. An emitter layer is disposed on the base layer. The collector electrode is disposed directly on a sidewall of the upper sub-collector layer.Type: ApplicationFiled: January 6, 2020Publication date: July 8, 2021Inventors: Chien-Rong YU, Shu-Hsiao TSAI, Jui-Pin CHIU
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Patent number: 10756625Abstract: An integrated module of acoustic wave device with active thermal compensation comprises a substrate, an acoustic wave filter, an active adjustment circuit and at least one variable capacitance device. The acoustic wave filter comprises a plurality of series acoustic wave resonators formed on the substrate, at least one shunt acoustic wave resonator formed on the substrate and a thermal sensing acoustic wave resonator. Each of the variable capacitance device is connected in parallel to one of the series and shunt acoustic wave resonators. The active adjustment circuit outputs an active thermal compensation signal correlated to a thermal variation sensed by the thermal sensing acoustic wave resonator to the variable capacitance device. The active thermal compensation signal induces a capacitance variation of the variable capacitance device such that the impact of the thermal variation to the acoustic wave device is compensated.Type: GrantFiled: June 27, 2017Date of Patent: August 25, 2020Assignee: WIN SEMICONDUCTORS CORP.Inventors: Re Ching Lin, Shu Hsiao Tsai, Cheng Kuo Lin, Chih-Feng Chiang, Fan Hsiu Huang, Tung-Yao Chou
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Patent number: 10727741Abstract: An acoustic wave filter having thermal sensing acoustic wave resonator comprises a substrate, a plurality of series acoustic wave resonators formed on the substrate, at least one shunt acoustic wave resonator formed on the substrate and a thermal sensing acoustic wave resonator. The thermal sensing acoustic wave resonator is one of a series acoustic wave resonator and a shunt acoustic wave resonator. Thereby the thermal sensing acoustic wave resonator plays dual roles of thermal sensing and acoustic wave filtering.Type: GrantFiled: June 27, 2017Date of Patent: July 28, 2020Assignee: WIN SEMICONDUCTORS CORP.Inventors: Re Ching Lin, Shu Hsiao Tsai, Cheng Kuo Lin, Fan Hsiu Huang, Chih-Feng Chiang, Tung-Yao Chou
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Patent number: 10553709Abstract: A heterojunction bipolar transistor, comprising an elongated base mesa, an elongated base electrode, two elongated emitters, an elongated collector, and two elongated collector electrodes. The elongated base electrode is formed on the base mesa along the long axis of the base mesa, and the base electrode has a base via hole at or near the center of the base electrode. The two elongated emitter are formed on the base mesa respectively at two opposite sides of the base electrode, and each of two emitters has an elongated emitter electrode formed on the emitter. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.Type: GrantFiled: January 19, 2018Date of Patent: February 4, 2020Assignee: WIN SEMICONDUCTORS CORP.Inventors: Jui-Pin Chiu, Shu-Hsiao Tsai, Rong-Hao Syu, Cheng-Kuo Lin
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Patent number: 10498310Abstract: A protective cover for an acoustic wave device and a fabrication method thereof, for protecting an acoustic wave device having a resonant area during a packaging operation so as to avoid molding compound flowing onto the resonant area of the acoustic wave device. The fabrication method comprises: defining a sacrificial area on the acoustic wave device; forming a sacrificial layer on the sacrificial area; covering a metal covering layer on the sacrificial layer and connecting a bottom rim of the metal covering layer to the acoustic wave device and forming an opening between the bottom rim of the metal covering layer and the acoustic wave device; and removing the sacrificial layer to form a cavity between the metal covering layer and the resonant area by using a chemical solution, wherein the chemical solution enters from the opening between the metal covering layer and the acoustic wave device.Type: GrantFiled: March 15, 2016Date of Patent: December 3, 2019Assignee: WIN SEMICONDUCTORS CORP.Inventors: Cheng-Kuo Lin, Shu-Hsiao Tsai, Rong-Hao Syu, Yi-Ling Liu, Re-Ching Lin, Pei-Chun Liao
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Patent number: 10453805Abstract: A chip stack having a protection structure for semiconductor device package, which comprises a first chip and a second chip stacked with each other, wherein said first chip has a first surface, said second chip has a second surface, said first surface and said second surface are two surfaces facing to each other, wherein at least one metal pillar is formed on at least one of said first surface and said second surface and connected with the other, at least one protection ring is formed on at least one of said first surface and said second surface and having a first gap with the other, and at least one electrical device is formed on at least one of said first surface and said second surface, wherein said at least one electrical device is located inside at least one of said at least one protection ring.Type: GrantFiled: May 5, 2016Date of Patent: October 22, 2019Assignee: WIN SEMICONDUCTORS CORP.Inventors: Pei-Chun Liao, Po-Wei Ting, Chih-Feng Chiang, Yu-Kai Wu, Yu-Fan Chang, Re-Ching Lin, Shu-Hsiao Tsai, Cheng-Kuo Lin