Patents by Inventor Shu-Hsiao TSAI

Shu-Hsiao TSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10298203
    Abstract: A chip stack having a protection structure for semiconductor device package comprises a first chip and a second chip stacked with each other. A first surface of the first chip and a second surface of the second chip are facing to each other. At least one metal pillar is formed on at least one of the first surface and the second surface and connected with the other. At least one protection ring is formed on at least one of the first surface and the second surface and having a first gap with the other. At least one electrical device is formed on at least one of the first surface and the second surface and is located inside at least one of the at least one protection ring, wherein the at least one electrical device includes a temperature sensor.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 21, 2019
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Pei-Chun Liao, Po-Wei Ting, Chih-Feng Chiang, Yu-Kai Wu, Yu-Fan Chang, Re-Ching Lin, Shu-Hsiao Tsai, Cheng-Kuo Lin
  • Patent number: 10103624
    Abstract: A thermal sensor circuit comprises a conversion circuit which is one of a buck DC-DC converter circuit and a boost DC-DC converter circuit, wherein the conversion circuit comprises an inductor and an output terminal. A thermal sensor senses a thermal variation correlated to a capacitance variation of the thermal sensor. The capacitance variation induces an internal parasitic capacitance variation of the inductor which is connected in parallel to the thermal sensor and results a variation of an energy stored in the inductor. Hence a variation of a converted circuit signal outputting by the output terminal is caused, wherein the variation of the converted circuit signal is correlated to the thermal variation.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: October 16, 2018
    Assignee: WIN Semiconductors Corp.
    Inventors: Re Ching Lin, Fan Hsiu Huang, Tung-Yao Chou, Cheng Kuo Lin, Shu Hsiao Tsai, Chih-Feng Chiang
  • Patent number: 9998087
    Abstract: An integrated structure of power amplifier and acoustic wave device comprises: a compound semiconductor epitaxial substrate including an epitaxial structure formed on a compound semiconductor substrate, a power amplifier upper structure formed on a top-side of a left part of the compound semiconductor epitaxial substrate, and a film bulk acoustic resonator formed on the top-side of a right part of the compound semiconductor epitaxial substrate; wherein the left part of the compound semiconductor epitaxial substrate and the power amplifier upper structure form a power amplifier; the right part of the compound semiconductor epitaxial substrate and the film bulk acoustic resonator form an acoustic wave device; the integrated structure of power amplifier and acoustic wave device on the same compound semiconductor epitaxial substrate is capable of reducing the component size, optimizing the impedance matching, and reducing the signal loss between power amplifier and acoustic wave device.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: June 12, 2018
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Shu-Hsiao Tsai, Re Ching Lin, Pei-Chun Liao, Cheng-Kuo Lin, Yung-Chung Chin
  • Patent number: 9991198
    Abstract: A layout method for compound semiconductor integrated circuits, comprising following steps of: forming a first metal layer within a first circuit layout area which intersects with a second circuit layout area at an intersection area on a compound semiconductor substrate; defining an adjacent crossover area including said intersection area and a peripheral adjacent area thereof; a first dielectric area located within said adjacent crossover area and intersected with at least part of said intersection area; forming a first dielectric block within said first dielectric area or forming said first dielectric block within said first dielectric area and a second dielectric block outside said first dielectric area, the thickness of said second dielectric block is no greater than and the thickness of at least part of said second dielectric block is smaller than the thickness of said first dielectric block; forming a second metal layer within said second circuit layout area.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: June 5, 2018
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Shu-Hsiao Tsai, Rong-Hao Syu, Yi-Ling Liu, Cheng-Kuo Lin
  • Publication number: 20180145159
    Abstract: A heterojunction bipolar transistor, comprising an elongated base mesa, an elongated base electrode, two elongated emitters, an elongated collector, and two elongated collector electrodes. The elongated base electrode is formed on the base mesa along the long axis of the base mesa, and the base electrode has a base via hole at or near the center of the base electrode. The two elongated emitter are formed on the base mesa respectively at two opposite sides of the base electrode, and each of two emitters has an elongated emitter electrode formed on the emitter. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.
    Type: Application
    Filed: January 19, 2018
    Publication date: May 24, 2018
    Inventors: Jui-Pin CHIU, Shu-Hsiao TSAI, Rong-Hao SYU, Cheng-Kuo LIN
  • Patent number: 9911837
    Abstract: A heterojunction bipolar transistor, comprising an elongated base mesa, an “H” shaped emitter, two base electrodes, an elongated collector, and two elongated collector electrodes. The “H” shaped emitter is formed on the base mesa and has two parallel bars connected by a cross-bar. Two elongated emitter electrodes are formed respectively on the two parallel bars of the “H” shaped emitter. The “H” shaped emitter has two recesses respectively on two opposite sides of the cross-bar between the two parallel bars. The two base electrodes are formed on the base mesa respectively at the two recesses of the “H” shaped emitter, each of which has a base via hole near a center of the base mesa. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: March 6, 2018
    Assignee: Win Semiconductors Corp.
    Inventors: Jui-Pin Chiu, Shu-Hsiao Tsai, Rong-Hao Syu, Cheng-Kuo Lin
  • Patent number: 9905610
    Abstract: An integrated structure of acoustic wave device and varactor comprises an acoustic wave device and a varactor formed on a first part and a second part of a semiconductor substrate respectively. The acoustic wave device comprises an acoustic wave device upper structure and a first part of a bottom epitaxial structure. The acoustic wave device upper structure is formed on the first part of the bottom epitaxial structure. The varactor comprises a varactor upper structure and a second part of the bottom epitaxial structure. The varactor upper structure is formed on the second part of the bottom epitaxial structure. The integrated structure of the acoustic wave device and the varactor formed on the same semiconductor substrate is capable of reducing the module size, optimizing the impedance matching, and reducing the signal loss between the varactor and the acoustic wave device.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: February 27, 2018
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Shu-Hsiao Tsai, Re Ching Lin, Pei-Chun Liao, Cheng-Kuo Lin, Yung-Chung Chin, Chih-Feng Chiang
  • Publication number: 20180006633
    Abstract: An integrated module of acoustic wave device with active thermal compensation comprises a substrate, an acoustic wave filter, an active adjustment circuit and at least one variable capacitance device. The acoustic wave filter comprises a plurality of series acoustic wave resonators formed on the substrate, at least one shunt acoustic wave resonator formed on the substrate and a thermal sensing acoustic wave resonator. Each of the variable capacitance device is connected in parallel to one of the series and shunt acoustic wave resonators. The active adjustment circuit outputs an active thermal compensation signal correlated to a thermal variation sensed by the thermal sensing acoustic wave resonator to the variable capacitance device. The active thermal compensation signal induces a capacitance variation of the variable capacitance device such that the impact of the thermal variation to the acoustic wave device is compensated.
    Type: Application
    Filed: June 27, 2017
    Publication date: January 4, 2018
    Inventors: Re Ching Lin, Shu Hsiao Tsai, Cheng Kuo Lin, Chih-Feng Chiang, Fan Hsiu Huang, Tung-Yao Chou
  • Publication number: 20180003570
    Abstract: An acoustic wave filter having thermal sensing acoustic wave resonator comprises a substrate, a plurality of series acoustic wave resonators formed on the substrate, at least one shunt acoustic wave resonator formed on the substrate and a thermal sensing acoustic wave resonator. The thermal sensing acoustic wave resonator is one of a series acoustic wave resonator and a shunt acoustic wave resonator. Thereby the thermal sensing acoustic wave resonator plays dual roles of thermal sensing and acoustic wave filtering.
    Type: Application
    Filed: June 27, 2017
    Publication date: January 4, 2018
    Inventors: Re Ching Lin, Shu Hsiao Tsai, Cheng Kuo Lin, Fan Hsiu Huang, Chih-Feng Chiang, Tung-Yao Chou
  • Publication number: 20180006556
    Abstract: A thermal sensor circuit comprises a conversion circuit which is one of a buck DC-DC converter circuit and a boost DC-DC converter circuit, wherein the conversion circuit comprises an inductor and an output terminal. A thermal sensor senses a thermal variation correlated to a capacitance variation of the thermal sensor. The capacitance variation induces an internal parasitic capacitance variation of the inductor which is connected in parallel to the thermal sensor and results a variation of an energy stored in the inductor. Hence a variation of a converted circuit signal outputting by the output terminal is caused, wherein the variation of the converted circuit signal is correlated to the thermal variation.
    Type: Application
    Filed: June 27, 2017
    Publication date: January 4, 2018
    Inventors: Re Ching Lin, Fan Hsiu Huang, Tung-Yao Chou, Cheng Kuo Lin, Shu Hsiao Tsai, Chih-Feng Chiang
  • Publication number: 20170272052
    Abstract: A protective cover for an acoustic wave device and a fabrication method thereof, for protecting an acoustic wave device having a resonant area on a surface of a substrate during a packaging operation so as to avoid molding compound flowing onto the resonant area of the acoustic wave device, wherein at least one electrical device is provided on the surface of the substrate and the at least one electrical device includes a temperature sensor. The acoustic wave device protection structure comprising: a metal covering layer, having a concave surface and a bottom rim, the bottom rim connected to the acoustic wave device and forming at least one opening between the bottom rim and the acoustic wave device, and the concave surface covering over the resonant area to form a cavity between the concave surface and the resonant area.
    Type: Application
    Filed: June 8, 2017
    Publication date: September 21, 2017
    Inventors: Cheng-Kuo Lin, Shu-Hsiao Tsai, Rong-Hao Syu, Yi-Ling Liu, Re-Ching Lin, Pei-Chun Liao, Chih-Feng Chiang
  • Publication number: 20170203959
    Abstract: A chip stack having a protection structure for semiconductor device package comprises a first chip and a second chip stacked with each other. A first surface of the first chip and a second surface of the second chip are facing to each other. At least one metal pillar is formed on at least one of the first surface and the second surface and connected with the other. At least one protection ring is formed on at least one of the first surface and the second surface and having a first gap with the other. At least one electrical device is formed on at least one of the first surface and the second surface and is located inside at least one of the at least one protection ring, wherein the at least one electrical device includes a temperature sensor.
    Type: Application
    Filed: March 30, 2017
    Publication date: July 20, 2017
    Inventors: PEI-CHUN LIAO, PO-WEI TING, CHIH-FENG CHIANG, YU-KAI WU, YU-FAN CHANG, RE-CHING LIN, SHU-HSIAO TSAI, CHENG-KUO LIN
  • Publication number: 20170170233
    Abstract: An integrated structure of acoustic wave device and varactor comprises an acoustic wave device and a varactor formed on a first part and a second part of a semiconductor substrate respectively. The acoustic wave device comprises an acoustic wave device upper structure and a first part of a bottom epitaxial structure. The acoustic wave device upper structure is formed on the first part of the bottom epitaxial structure. The varactor comprises a varactor upper structure and a second part of the bottom epitaxial structure. The varactor upper structure is formed on the second part of the bottom epitaxial structure. The integrated structure of the acoustic wave device and the varactor formed on the same semiconductor substrate is capable of reducing the module size, optimizing the impedance matching, and reducing the signal loss between the varactor and the acoustic wave device.
    Type: Application
    Filed: February 28, 2017
    Publication date: June 15, 2017
    Inventors: Shu-Hsiao TSAI, Re Ching LIN, Pei-Chun LIAO, Cheng-Kuo LIN, Yung-Chung CHIN
  • Publication number: 20170162518
    Abstract: A chip stack having a protection structure for semiconductor device package, which comprises a first chip and a second chip stacked with each other, wherein said first chip has a first surface, said second chip has a second surface, said first surface and said second surface are two surfaces facing to each other, wherein at least one metal pillar is formed on at least one of said first surface and said second surface and connected with the other, at least one protection ring is formed on at least one of said first surface and said second surface and having a first gap with the other, and at least one electrical device is formed on at least one of said first surface and said second surface, wherein said at least one electrical device is located inside at least one of said at least one protection ring.
    Type: Application
    Filed: May 5, 2016
    Publication date: June 8, 2017
    Inventors: PEI-CHUN LIAO, PO-WEI TING, CHIH-FENG CHIANG, YU-KAI WU, YU-FAN CHANG, RE-CHING LIN, SHU-HSIAO TSAI, CHENG-KUO LIN
  • Patent number: 9653516
    Abstract: An integrated structure of power amplifier and acoustic wave device comprises: a compound semiconductor epitaxial substrate, a power amplifier upper structure formed on a first side of said compound semiconductor epitaxial substrate, and a film bulk acoustic resonator formed on a second side of said compound semiconductor epitaxial substrate; wherein forming an epitaxial structure on a compound semiconductor substrate to form said compound semiconductor epitaxial substrate; wherein said first side of said compound semiconductor epitaxial substrate and said power amplifier upper structure form a power amplifier; said second side of said compound semiconductor epitaxial substrate and said film bulk acoustic resonator form an acoustic wave device; the integrated structure of power amplifier and acoustic wave device on the same compound semiconductor epitaxial substrate is capable of reducing the component size, optimizing the impedance matching, and reducing the signal loss between power amplifier and acoustic w
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: May 16, 2017
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Shu-Hsiao Tsai, Re Ching Lin, Pei-Chun Liao, Cheng-Kuo Lin, Yung-Chung Chin
  • Publication number: 20170134000
    Abstract: An integrated structure of power amplifier and acoustic wave device comprises: a compound semiconductor epitaxial substrate, a power amplifier upper structure formed on a first side of said compound semiconductor epitaxial substrate, and a film bulk acoustic resonator formed on a second side of said compound semiconductor epitaxial substrate; wherein forming an epitaxial structure on a compound semiconductor substrate to form said compound semiconductor epitaxial substrate; wherein said first side of said compound semiconductor epitaxial substrate and said power amplifier upper structure form a power amplifier; said second side of said compound semiconductor epitaxial substrate and said film bulk acoustic resonator form an acoustic wave device; the integrated structure of power amplifier and acoustic wave device on the same compound semiconductor epitaxial substrate is capable of reducing the component size, optimizing the impedance matching, and reducing the signal loss between power amplifier and acoustic w
    Type: Application
    Filed: January 25, 2017
    Publication date: May 11, 2017
    Inventors: Shu-Hsiao TSAI, Re Ching LIN, Pei-Chun LIAO, Cheng-Kuo LIN, Yung-Chung CHIN
  • Publication number: 20170110400
    Abstract: A layout method for compound semiconductor integrated circuits, comprising following steps of: forming a first metal layer within a first circuit layout area which intersects with a second circuit layout area at an intersection area on a compound semiconductor substrate; defining an adjacent crossover area including said intersection area and a peripheral adjacent area thereof; a first dielectric area located within said adjacent crossover area and intersected with at least part of said intersection area; forming a first dielectric block within said first dielectric area or forming said first dielectric block within said first dielectric area and a second dielectric block outside said first dielectric area, the thickness of said second dielectric block is no greater than and the thickness of at least part of said second dielectric block is smaller than the thickness of said first dielectric block; forming a second metal layer within said second circuit layout area.
    Type: Application
    Filed: March 10, 2016
    Publication date: April 20, 2017
    Inventors: Shu-Hsiao TSAI, Rong-Hao SYU, Yi-Ling LIU, Cheng-Kuo LIN
  • Publication number: 20170077899
    Abstract: A protective cover for an acoustic wave device and a fabrication method thereof, for protecting an acoustic wave device having a resonant area during a packaging operation so as to avoid molding compound flowing onto the resonant area of the acoustic wave device. The fabrication method comprises: defining a sacrificial area on the acoustic wave device; forming a sacrificial layer on the sacrificial area; covering a metal covering layer on the sacrificial layer and connecting a bottom rim of the metal covering layer to the acoustic wave device and forming an opening between the bottom rim of the metal covering layer and the acoustic wave device; and removing the sacrificial layer to form a cavity between the metal covering layer and the resonant area by using a chemical solution, wherein the chemical solution enters from the opening between the metal covering layer and the acoustic wave device.
    Type: Application
    Filed: March 15, 2016
    Publication date: March 16, 2017
    Inventors: Cheng-Kuo Lin, Shu-Hsiao Tsai, Rong-Hao Syu, Yi-Ling Liu, Re-Ching Lin, Pei-Chun Liao
  • Publication number: 20160322482
    Abstract: A heterojunction bipolar transistor, comprising an elongated base mesa, an “H” shaped emitter, two base electrodes, an elongated collector, and two elongated collector electrodes. The “H” shaped emitter is formed on the base mesa and has two recesses respectively on two opposite sides of the “H” shape, and the emitter has two elongated emitter electrodes formed on the “H” shaped emitter. The two base electrodes are formed on the base mesa respectively at the two recesses of the “H” shaped emitter, and each of the base electrodes has a base via hole at or near the center of the base mesa. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.
    Type: Application
    Filed: July 7, 2016
    Publication date: November 3, 2016
    Inventors: Jui-Pin CHIU, Shu-Hsiao TSAI, Rong-Hao SYU, Cheng-Kuo LIN
  • Publication number: 20160247797
    Abstract: A layout structure of HBTs comprising one or more HBTs, each of which comprises a base electrode, an emitter electrode, and a collector electrode. A passive layer, a first dielectric layer, a collector redistribution layers, one or more emitter copper pillars, and one or more collector copper pillars are formed above the one or more HBTs. The passive layer comprises a collector and an emitter pads. The first dielectric layer has one or more emitter and collector via holes. The emitter copper pillar is disposed on the emitter via hole and forms an electrical connection to the emitter electrode. The collector copper pillar is disposed on the collector redistribution layer and forms electrical connection to the collector electrode. The layout design of the emitter and collector copper pillars is therefore flexible, and the heat dissipation efficiency is improved.
    Type: Application
    Filed: April 29, 2016
    Publication date: August 25, 2016
    Inventors: Shu-Hsiao TSAI, Hsiu-Chen CHANG, Shinichiro TAKATANI, Cheng-Kuo LIN