Abstract: An electronic device includes a flexible substrate and a conductive wire. The conductive wire is disposed on the flexible substrate and includes a metal portion and a plurality of openings disposed in the metal portion. The metal portion includes a plurality of extending portions and a plurality of joint portions, and each of the openings is surrounded by two of the plurality of extending portions and two of the plurality of joint portions. A ratio of a sum of widths of the plurality of extending portions to a sum of widths of the plurality of joint portions is in a range from 0.8 to 1.2.

Abstract: This disclosure relates to a stretchable composite electrode and a fabricating method thereof, and particularly relates to a stretchable composite electrode including a silver nanowire layer and a flexible polymer film and a fabricating method thereof.

Abstract: A firing control system with multiple safeties is disclosed. It comprises a base, a return spring, a firing pin releaser, and a trigger connecting bar. The trigger connecting bar is connected with the trigger of the pistol and has a firing safety portion with a T shape. The design of the firing safety portion with a limit protrusion portion of the firing pin releaser of the present invention form a safety mechanism for unintentional discharge of the pistol, which improves the problem that the existing improved products are easy to cause the pistol to fire under an unfired state.

Abstract: A method for fabricating semiconductor devices includes forming channel regions over a substrate. The channel regions, in parallel with one another, extend along a first lateral direction. Each channel region includes at least a respective pair of epitaxial structures. The method includes forming a gate structure over the channel regions, wherein the gate structure extends along a second lateral direction. The method includes removing, through a first etching process, a portion of the gate structure that was disposed over a first one of the channel regions. The method includes removing, through a second etching process, a portion of the first channel region. The second etching process includes one silicon etching process and one silicon oxide deposition process. The method includes removing, through a third etching process controlled based on a pulse signal, a portion of the substrate that was disposed below the removed portion of the first channel region.

Abstract: A method for automatically setting addresses suitable for an RS485 system is provided. The RS485 system includes a host device and a plurality of slave devices. The method includes the following stages. The host device confirms that there are no addresses of the slave devices in a database. The slave devices are turned on in sequence. The slave devices calculate their own respective power-on times. The slave device enter an idle state during the period associated with the power-on time. Only one of the slave devices sends the power-on time to the host device when said slave device leaves the idle state. The host device sets the address of said slave device according to the power-on time when said slave device leaves the idle state.

Abstract: A semiconductor die included in a semiconductor die package may include a plurality of decoupling trench capacitor regions in a device region of the semiconductor die. At least two or more of the decoupling trench capacitor regions include decoupling trench capacitor structures having different depths. The depths of the decoupling trench capacitor structures in the decoupling trench capacitor regions may be selected to provide sufficient capacitance so as to satisfy circuit decoupling parameters for circuits of the semiconductor die package, while reducing the likelihood of warping, breaking, and/or cracking of the semiconductor die package.

Abstract: A high-throughput automated preprocessing method and a system are applied to a nucleic acid preprocessing apparatus including a control system, a sample transfer area, a nucleic acid extraction area, and a reagent setup area. The control system includes a user interface and guides a user to set up on the user interface. In the sample transfer area, the method includes steps of: a user selecting a sampling tube type, a test protocol and an extraction protocol on the user interface, and the control system performing a sample transfer task. In the nucleic acid extraction area, the method includes steps of: the control system performing a nucleic acid extraction task based on the selected extraction protocol. In the reagent setup area, the method includes steps of: the control system performing a reagent deployment task based on the selected test protocol, and the control system performing a nucleic acid transfer task.

Abstract: An eFuse structure is provided, the structure comprising a first fuse link having a first side. The first fuse link having a first indentation on the first side, the first indentation having a non-linear profile. A first dummy structure may be laterally spaced from the first indentation of the first fuse link.

Abstract: A semiconductor device is provided. The semiconductor device comprises a first semiconductor die comprising a first capacitor, and a second semiconductor die in contact with the first semiconductor die and comprises a diode. The first semiconductor die and the second semiconductor die are arranged along a first direction, and a diode is configured to direct electrons accumulated at the first capacitor to a ground.

Abstract: Disclosed is an electronic device having a display region and a peripheral region adjacent to the display region. The electronic device includes a first electrode disposed in the display region, a second electrode disposed in the display region, a circuit module disposed in the peripheral region, a first electrical trace, and a second electrical trace electrically insulated from the first electrical trace. The circuit module is electrically connected to the first electrode through the first electrical trace and provides a first driving voltage to the first electrical trace. The circuit module is electrically connected to the second electrode through the second electrical trace and provides a second driving voltage to the second electrical trace, and the first driving voltage is different from the second driving voltage. In a top view, the first electrical trace at least partially overlaps the second electrical trace.

Abstract: A continuous manufacturing equipment of an elastic three-dimensional fabric and a continuous manufacturing method thereof are disclosed. The continuous manufacturing equipment includes: a film conveying device having a thermal melting film and a conveying mechanism; a cutting device used for cutting a plurality of cutting gaps on the thermal melting film; a first fabric laminating device adhering an outer fabric on one surface of the thermal melting film; and a second fabric laminating device adhering an elastic fabric on another surface of the thermal melting film in a manner of elastically stretching and then elastically recovering. As such, effects of automatic, continuous, and simple steps in manufacturing and having a high yield rate are provided.

Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.

Abstract: Disclosed herein are methods for inhibiting growth of oral pathogenic bacteria and alleviating an oral pathogenic bacteria-associated disorder using a culture of at least one lactic acid bacterial strain selected from the group consisting of Lactobacillus rhamnosus MP108 which is deposited at the China General Microbiological Culture Collection Center (CGMCC) under an accession number CGMCC 21225, and Lactobacillus paracasei MP137 which is deposited at the CGMCC under an accession number CGMCC 21224.

Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes receiving a workpiece including a first semiconductor fin and a second semiconductor fin penetrating from a substrate and separated by a first isolation feature, and a gate structure intersecting the first semiconductor fin and the second semiconductor fin. The method also includes removing the gate structure and portions of the first semiconductor fin, the second semiconductor fin, and the first isolation feature disposed directly under the gate structure to form a fin isolation trench, forming a dielectric layer over the workpiece to substantially fill the fin isolation trench, and planarizing the dielectric layer to form a fin isolation structure in the fin isolation trench.

Abstract: Various embodiments of the present disclosure provide a semiconductor device structure.

Abstract: The present disclosure provides a semiconductor device, including a first semiconductor structure and a second semiconductor structure. Each of the first semiconductor structure and the second semiconductor structure includes a substrate; a through silicon via, penetrating the substrate; and a deep trench capacitor, disposed in the substrate, separated from the TSV by a distance. The deep trench capacitor includes a stack, including a dielectric layer between a pair of conductive layers in a trench; and an insulating layer, covering the stack and the trench. The insulating layer surround a plurality of voids in the trench.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a plurality of conductive contacts overlying a semiconductor substrate. A plurality of first conductive wires is disposed on the plurality of conductive contacts. A plurality of conductive vias overlies the first conductive wires. An etch stop structure is disposed on the first conductive wires. The plurality of conductive vias extend through the etch stop structure. The etch stop structure includes a first etch stop layer, a first insulator layer, and a second etch stop layer. The first insulator layer is disposed between the first etch stop layer and the second etch stop layer.

Abstract: Various embodiments of the present application are directed towards an integrated chip (IC). The IC comprises a trench capacitor overlying a substrate. The trench capacitor comprises a plurality of capacitor electrode structures, a plurality of warping reduction structures, and a plurality of capacitor dielectric structures. The plurality of capacitor electrode structures, the plurality of warping reduction structures, and the plurality of capacitor dielectric structures are alternatingly stacked and define a trench segment that extends vertically into the substrate. The plurality of capacitor electrode structures comprise a metal component and a nitrogen component. The plurality of warping reduction structures comprise the metal component, the nitrogen component, and an oxygen component.

Abstract: Provided antibodies or antigen-binding fragment thereof specific for the variant exon v9 of the CD44 gene (CD44v9), antibody-drug-conjugate (ADC), and other derivative comprising the antibodies or antigen-binding fragment. Provided nucleic acid molecules encoding the same, and methods of making the same. Further provided pharmaceutical compositions comprising the same, and the use of the same in treating diseases or in the manufacture of a medicament for the treatment of the diseases, such as cancer.

Abstract: A part processing planning method includes the following steps. Firstly, a specific tolerance of a nominal size of a part is obtained. Then, a predetermined tolerance of each of processes is obtained. Then, using a process dimension chain establishing technique, at least one predetermined tolerance associated with the specification tolerance from the predetermined tolerances is obtained. Then, at least one predetermined tolerance associated with the specification tolerance is accumulated to obtain a size cumulative tolerance. Then, whether the size cumulative tolerance meets the specification tolerance is determined. Then, at least one predetermined tolerance associated with the specification tolerance is re-allocated when the cumulative tolerance does not meet the specification tolerance, such that the size cumulative tolerance is within the specification tolerance.