Abstract: A memory device that operates at high speed is provided. The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.

Abstract: A semiconductor device having favorable electrical characteristics is provided.

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j?2, the jth sub memory cell is arranged over the j-lth sub memory cell.

Abstract: A memory device that operates at high speed is provided. The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.

Abstract: A semiconductor device in which an electrification phenomenon that leads to characteristic fluctuations, element deterioration, abnormality in shape, or dielectric breakdown is inhibited is provided. The semiconductor device includes a first region and a second region over the same plane. The first region includes a transistor. The second region includes a dummy transistor. The transistor includes a first wiring layer, a semiconductor layer including an oxide and provided above the first wiring layer, a second wiring layer provided above the semiconductor layer, and a third wiring layer provided above the second wiring layer. The dummy transistor has the same area as one or more selected from the first wiring layer, the second wiring layer, the semiconductor layer, and the third wiring layer.

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j?2, the jth sub memory cell is arranged over the j?1th sub memory cell.

Abstract: A semiconductor device enabling high integration is provided. The semiconductor device includes a plug, two capacitors, and two transistors sharing one oxide semiconductor. Each of the transistors includes a stacked-layer structure of a gate insulator and a gate electrode over the oxide semiconductor and an insulator in contact with a side surface of the gate electrode. An opening between the two gate electrodes exposes the insulators in contact with the side surfaces of the gate electrodes, and the plug is in the opening. The capacitor is directly provided over the oxide semiconductor. The side surface area of the capacitor is larger than the projected area of the capacitor.

Abstract: A data reading error is reduced. A memory cell array in a storage device includes a write word line, a read word line, a write bit line, a read bit line, a source line, and a gain cell. For example, a read transistor in the gain cell can include a metal oxide in a channel formation region. A cancel circuit is electrically connected to the read bit line. The cancel circuit has a function of supplying, to the read bit line, current for canceling leakage current supplied to the read bit line from the gain cell in a non-selected state. In read operation, a potential change of the read bit line due to leakage current is compensated for by the current from the cancel circuit, so that a data reading error is reduced.

Abstract: A semiconductor device including a first oxide including a first region and a second region adjacent to each other and a third region and a fourth region with the first region and the second region sandwiched between the third region and the fourth region, a second oxide over the first region, a first insulator over the second oxide, a first conductor over the first insulator, a second insulator over the second oxide and on side surfaces of the first insulator and the first conductor, a third insulator over the second region and on a side surface of the second insulator, a second conductor over the second region with the third insulator positioned between the second region and the second conductor and on the side surface of the second insulator with the third insulator positioned between the side surface of the second insulator and the second conductor, and a fourth insulator covering the first oxide, the second oxide, the first insulator, the first conductor, the second insulator, the third insulator, and th

Abstract: A semiconductor device that can be highly integrated is provided. The semiconductor device includes a first transistor, a second transistor, a first capacitor, and a second capacitor. The first transistor includes an oxide over a first insulator, a second insulator over the oxide, a first conductor over the second insulator, a third insulator over the first conductor, a fourth insulator in contact with the second insulator, the first conductor, and the third insulator, and a fifth insulator in contact with the fourth insulator. The second transistor includes an oxide over the first insulator, a sixth insulator over the oxide, a second conductor over the sixth insulator, a seventh insulator over the second conductor, an eighth insulator in contact with the sixth insulator, the second conductor, and the seventh insulator, and a ninth insulator in contact with the eighth insulator. The first capacitor includes an oxide, a tenth insulator over the oxide, and a third conductor over the tenth insulator.

Abstract: A memory device that operates at high speed is provided. The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.

Abstract: An electric power charge and discharge system for an electronic device having a battery, by which the electronic device can be used for a long period of time. In a wireless communication device including a wireless driving portion including a first battery and a wireless charging portion including a second battery, the first battery is charged by electric power from a fixed power supply and the second battery is charged by using electromagnetic waves existing in an external space. Further, the first battery and the second battery are discharged alternately, and during a period in which the first battery is discharged, the second battery is charged.

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes an oxide in a channel formation region; the semiconductor device includes a first transistor, a second transistor, a first wiring, a second wiring, and a third wiring, and the first transistor includes the oxide over a first insulator, a second insulator over the oxide, a first conductor over the second insulator, a third insulator over the first conductor, and a fourth insulator in contact with the second insulator, the first conductor, and the third insulator. The second transistor includes the oxide over a fifth insulator, a sixth insulator over the oxide, a second conductor over the sixth insulator, a seventh insulator over the second conductor, and an eighth insulator in contact with the sixth insulator, the second conductor, and the seventh insulator.

Abstract: To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.

Abstract: A memory device includes a memory cell, a replica cell, a read circuit, a write wordline, a read wordline, a dummy read wordline, a write bitline, a read bitline, a reference bitline, a sourceline, and a first wiring. The memory cell is electrically connected to the write wordline, the read wordline, the write bitline, the read bitline, and the sourceline. The read circuit outputs a potential based on the result of comparing the potential of the reference bitline and the potential of the read bitline. The replica cell includes a first transistor and a second transistor. The first transistor and the second transistor are electrically connected to each other in series between the bitline and the sourceline. A gate of the first transistor and a gate of the second transistor are electrically connected to a dummy read wordline and the first wiring, respectively.

Abstract: A semiconductor device including a first oxide including a first region and a second region adjacent to each other and a third region and a fourth region with the first region and the second region sandwiched between the third region and the fourth region, a second oxide over the first region, a first insulator over the second oxide, a first conductor over the first insulator, a second insulator over the second oxide and on side surfaces of the first insulator and the first conductor, a third insulator over the second region and on a side surface of the second insulator, a second conductor over the second region with the third insulator positioned between the second region and the second conductor and on the side surface of the second insulator with the third insulator positioned between the side surface of the second insulator and the second conductor, and a fourth insulator covering the first oxide, the second oxide, the first insulator, the first conductor, the second insulator, the third insulator, and th

Abstract: A semiconductor device in which an electrification phenomenon that leads to characteristic fluctuations, element deterioration, or dielectric breakdown is inhibited is provided. A first transistor, a second transistor, a third transistor, and a fourth transistor are included over a substrate; the fourth transistor includes a first conductor, a second conductor, a third conductor, and an oxide semiconductor; the first conductor is electrically connected to the semiconductor substrate through the first transistor; the second conductor is electrically connected to the semiconductor substrate through the first transistor; the third conductor is electrically connected to the semiconductor substrate through the first transistor; and the fourth conductor is electrically connected to the semiconductor substrate through the first transistor.

Abstract: An electric power charge and discharge system for an electronic device having a battery, by which the electronic device can be used for a long period of time. In a wireless communication device including a wireless driving portion including a first battery and a wireless charging portion including a second battery, the first battery is charged by electric power from a fixed power supply and the second battery is charged by using electromagnetic waves existing in an external space. Further, the first battery and the second battery are discharged alternately, and during a period in which the first battery is discharged, the second battery is charged.

Abstract: To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.

Abstract: An electric power charge and discharge system for an electronic device having a battery, by which the electronic device can be used for a long period of time. In a wireless communication device including a wireless driving portion including a first battery and a wireless charging portion including a second battery, the first battery is charged by electric power from a fixed power supply and the second battery is charged by using electromagnetic waves existing in an external space. Further, the first battery and the second battery are discharged alternately, and during a period in which the first battery is discharged, the second battery is charged.