Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j?2, the jth sub memory cell is arranged over the j?1th sub memory cell.

Abstract: A novel storage device and a novel semiconductor device are provided. In the storage device, a cell array including a plurality of memory cells is stacked above a control circuit, and the cell array operates separately in a plurality of blocks. Furthermore, a plurality of electrodes are included between the control circuit and the cell array. The electrode is provided for a corresponding block to overlap with the block, and a potential of the electrode can be changed for each block. The electrode has a function of aback gate of a transistor included in the memory cell, and a potential of the electrode is changed for each block, whereby the electrical characteristics of the transistor included in the memory cell can be changed. Moreover, the electrode can reduce noise caused in the control circuit.

Abstract: A novel memory device is provided. A first cell array including a plurality of memory cells and a second cell array including a plurality of memory cells are stacked. One of two bit lines of a first bit line pair is electrically connected to A memory cells of the first cell array, and the other of the two bit lines of the first bit line pair is electrically connected to D memory cells of the second cell array. One of two bit lines of a second bit line pair is electrically connected to B memory cells of the first cell array and F memory cells of the second cell array, and the other of the two bit lines of the second bit line pair is electrically connected to C memory cells of the first cell array and E memory cells of the second cell array. The first bit line pairs and the second bit line pairs are alternately provided.

Abstract: A data reading error is reduced. A memory cell array in a storage device includes a write word line, a read word line, a write bit line, a read bit line, a source line, and a gain cell. For example, a read transistor in the gain cell can include a metal oxide in a channel formation region. A cancel circuit is electrically connected to the read bit line. The cancel circuit has a function of supplying, to the read bit line, current for canceling leakage current supplied to the read bit line from the gain cell in a non-selected state. In read operation, a potential change of the read bit line due to leakage current is compensated for by the current from the cancel circuit, so that a data reading error is reduced.

Abstract: An electric power charge and discharge system for an electronic device having a battery, by which the electronic device can be used for a long period of time. In a wireless communication device including a wireless driving portion including a first battery and a wireless charging portion including a second battery, the first battery is charged by electric power from a fixed power supply and the second battery is charged by using electromagnetic waves existing in an external space. Further, the first battery and the second battery are discharged alternately, and during a period in which the first battery is discharged, the second battery is charged.

Abstract: A semiconductor device enabling high integration is provided. The semiconductor device includes a plug, two capacitors, and two transistors sharing one oxide semiconductor. Each of the transistors includes a stacked-layer structure of a gate insulator and a gate electrode over the oxide semiconductor and an insulator in contact with a side surface of the gate electrode. An opening between the two gate electrodes exposes the insulators in contact with the side surfaces of the gate electrodes, and the plug is in the opening. The capacitor is directly provided over the oxide semiconductor. The side surface area of the capacitor is larger than the projected area of the capacitor.

Abstract: A semiconductor device that can be highly integrated is provided. The semiconductor device includes a first transistor, a second transistor, a first capacitor, and a second capacitor. The first transistor includes an oxide over a first insulator, a second insulator over the oxide, a first conductor over the second insulator, a third insulator over the first conductor, a fourth insulator in contact with the second insulator, the first conductor, and the third insulator, and a fifth insulator in contact with the fourth insulator. The second transistor includes an oxide over the first insulator, a sixth insulator over the oxide, a second conductor over the sixth insulator, a seventh insulator over the second conductor, an eighth insulator in contact with the sixth insulator, the second conductor, and the seventh insulator, and a ninth insulator in contact with the eighth insulator. The first capacitor includes an oxide, a tenth insulator over the oxide, and a third conductor over the tenth insulator.

Abstract: A highly reliable semiconductor device capable of retaining data for a long period is provided. The transistor includes a first gate electrode, a first gate insulator over the first gate electrode, a first oxide and a second oxide over the first gate insulator, a first conductor over the first oxide, a second conductor over the second oxide, a third oxide covering the first gate insulator, the first oxide, the first conductor, the second oxide, and the second conductor, a second gate insulator over the third oxide, and a second gate electrode over the second gate insulator. An end portion of the second gate electrode is positioned between an end portion of the first conductor and an end portion of the second conductor in a channel length direction.

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j?2, the jth sub memory cell is arranged over the j-1th sub memory cell.

Abstract: A data reading error is reduced. A memory cell array in a storage device includes a write word line, a read word line, a write bit line, a read bit line, a source line, and a gain cell. For example, a read transistor in the gain cell can include a metal oxide in a channel formation region. A cancel circuit is electrically connected to the read bit line. The cancel circuit has a function of supplying, to the read bit line, current for canceling leakage current supplied to the read bit line from the gain cell in a non-selected state. In read operation, a potential change of the read bit line due to leakage current is compensated for by the current from the cancel circuit, so that a data reading error is reduced.

Abstract: A memory device includes a memory cell, a replica cell, a read circuit, a write wordline, a read wordline, a dummy read wordline, a write bitline, a read bitline, a reference bitline, a sourceline, and a first wiring. The memory cell is electrically connected to the write wordline, the read wordline, the write bitline, the read bitline, and the sourceline. The read circuit outputs a potential based on the result of comparing the potential of the reference bitline and the potential of the read bitline. The replica cell includes a first transistor and a second transistor. The first transistor and the second transistor are electrically connected to each other in series between the bitline and the sourceline. A gate of the first transistor and a gate of the second transistor are electrically connected to a dummy read wordline and the first wiring, respectively.

Abstract: A favorable semiconductor device for miniaturization and high integration is provided. One embodiment of the present invention includes a first oxide including a first region and second region adjacent to each other, a third region and a fourth region with the first region and the second region provided therebetween, a second oxide over the first region, a first insulator over the second oxide, a first conductor over the first insulator, a second insulator over the second oxide and on side surfaces of the first insulator and the first conductor, a third insulator over the second region and on a side surface of the second insulator, and a second conductor over the second region with the third insulator provided therebetween. A part of the third insulator is positioned between the second conductor and the side surface of the second insulator.

Abstract: To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.

Abstract: A semiconductor device including a first oxide including a first region and a second region adjacent to each other and a third region and a fourth region with the first region and the second region sandwiched between the third region and the fourth region, a second oxide over the first region, a first insulator over the second oxide, a first conductor over the first insulator, a second insulator over the second oxide and on side surfaces of the first insulator and the first conductor, a third insulator over the second region and on a side surface of the second insulator, a second conductor over the second region with the third insulator positioned between the second region and the second conductor and on the side surface of the second insulator with the third insulator positioned between the side surface of the second insulator and the second conductor, and a fourth insulator covering the first oxide, the second oxide, the first insulator, the first conductor, the second insulator, the third insulator, and th

Abstract: A semiconductor device in which stored data can be held even when power is not supplied and there is no limitation on the number of writing operations is provided. A semiconductor device is formed using a material which can sufficiently reduce the off-state current of a transistor, such as an oxide semiconductor material that is a wide-gap semiconductor. When a semiconductor material which can sufficiently reduce the off-state current of a transistor is used, the semiconductor device can hold data for a long period. In addition, by providing a capacitor or a noise removal circuit electrically connected to a write word line, a signal such as a short pulse or a noise input to a memory cell can be reduced or removed. Accordingly, a malfunction in which data written into the memory cell is erased when a transistor in the memory cell is instantaneously turned on can be prevented.

Abstract: To provide a semiconductor device that is not easily damaged by ESD in a manufacturing process thereof. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided to overlap with a dicing line. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided around the semiconductor device such as a transistor. The layer may be in a floating state or may be supplied with a specific potential.

Abstract: A memory device includes a memory cell, a replica cell, a read circuit, a write wordline, a read wordline, a dummy read wordline, a write bitline, a read bitline, a reference bitline, a sourceline, and a first wiring. The memory cell is electrically connected to the write wordline, the read wordline, the write bitline, the read bitline, and the sourceline. The read circuit outputs a potential based on the result of comparing the potential of the reference bitline and the potential of the read bitline. The replica cell includes a first transistor and a second transistor. The first transistor and the second transistor are electrically connected to each other in series between the bitline and the sourceline. A gate of the first transistor and a gate of the second transistor are electrically connected to a dummy read wordline and the first wiring, respectively.

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j?2, the jth sub memory cell is arranged over the j-1th sub memory cell. [Selected Drawing] FIG.

Abstract: A transistor having favorable electrical characteristics. A transistor suitable for miniaturization. A transistor having a high switching speed. One embodiment of the present invention is a semiconductor device that includes a transistor. The transistor includes an oxide semiconductor, a gate electrode, and a gate insulator. The oxide semiconductor includes a first region in which the oxide semiconductor and the gate electrode overlap with each other with the gate insulator positioned therebetween. The transistor has a threshold voltage higher than 0 V and a switching speed lower than 100 nanoseconds.

Abstract: In a logic circuit including transistors with the same conductivity, a reduction in output voltage is prevented with use of at least three transistors and a capacitor. With use of an oxide semiconductor in a semiconductor layer of the transistor, a logic circuit with high output voltage and high withstand voltage is achieved. With use of the logic circuit, a semiconductor device with high output voltage and high withstand voltage is achieved.