Abstract: This invention provides two circuit embodiments for a whole chip electrostatic discharge, ECD, protection scheme. It also includes a method for whole chip ESD protection. This invention relates to distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths. The advantage of this invention is the ability to create a parallel discharge path to ground in order to discharge the damaging ESD current quickly so as to avoid circuit damage. The two circuit embodiments show how the protection circuits of this invention at both the unzapped I/O pads and the zapped I/O pad are connected in a parallel circuit for discharging ESD currents quickly. These protection embodiments require a small amount of semiconductor area, since the smaller protection circuits are distributed and placed at the locations of each I/O pad.

Abstract: The present invention provides an ESD protection component, comprising at least two MOS field effect transistors (FETs) of a first conductivity type and a first well having a first conductivity type. The two MOS FETs have two parallel gates formed on a first semiconductive layer having a second conductivity type. The first well formed on the first semiconductive layer is comprised of a connecting area formed between the MOS FETs, two parallel extension areas formed perpendicular to the gates of the MOS FETs, and a first doping area of the second conductivity type formed in the connecting area. Two SCR are formed with drains of the MOS FETs, the first semiconductive layer, the first well and the first doping region. With the combination of the SCR and NMOS FET, ESD protection efficiency can be substantially enhanced.

Abstract: A stacked-gate flash memory cell is provided having step-shaped poly-gates with increased overlap area between them in order to increase the coupling ratio and hence the program speed of the cell. The floating gate is first formed with a step and the intergate dielectric is conformally shaped thereon followed by the forming of the control gate thereon. The increase in the-overlap area can be achieved by forming gates with multiply connected surfaces of different shapes.

Abstract: A method is provided for forming a highly dense stacked gate flash memory cell with a structure having multi floating gates that can assume 4 states and, therefore, store 2 bits at the same time. This is accomplished by providing a semiconductor substrate having gate oxide formed thereon, and shallow trench isolation and a p-well formed therein. A layer of nitride is next formed over the substrate and an opening formed therein. Polysilicon floating gate spacers are formed in the opening. A dielectric layer is then formed over the floating gates followed by the forming of a control gate. The adjacent nitride layer is then removed leaving a multi-level structure comprising a control gate therebetween multi floating gates with the intervening dielectric layer.

Abstract: A multi-level metal interconnect structure and method for forming the same for improving a resistance of CMOS transistors to electrostatic discharge (ESD) transient events is disclosed. A semiconductor device including at least one NMOS transistor electrically connected along at least one circuit pathway to an input/output signal source and a reference voltage potential; and, electrically connecting at least the input/output signal source to the at least one NMOS transistor with a metal interconnect line extended in length by compacting at least a portion of the metal interconnect line length portion into a serpentine shape within a predetermined volume of the semiconductor device.

Abstract: This invention provides two circuit embodiments for a whole chip electrostatic discharge, ECD, protection scheme. It also includes a method for whole chip ESD protection. This invention relates to distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths. The advantage of this invention is the ability to create a parallel discharge path to ground in order to discharge the damaging ESD current quickly so as to avoid circuit damage. The two circuit embodiments show how the protection circuits of this invention at both the unzapped I/O pads and the zapped I/O pad are connected in a parallel circuit for discharging ESD currents quickly. These protection embodiments require a small amount of semiconductor area, since the smaller protection circuits are distributed and placed at the locations of each I/O pad.

Abstract: A new method is provided for the creation of an aluminum contact pad. A layer of passivation is created over the surface of a substrate, an opening is created through the layer of passivation. A layer of aluminum is deposited over the surface of the deposited layer of passivation, filling the opening that has been created there-through. The deposited layer of aluminum is then polished down to the surface of the layer of passivation, leaving the deposited aluminum in place inside the opening created through the layer of passivation for purposes of serving as a contact pad.

Abstract: A new electrostatic discharge protection device is achieved. A p-well region is in a semiconductor substrate. An n+ region in the p-well region is connected to a first voltage supply. An n-well region in the p-well region is spaced from the n+ region such that a depletion region will extend therebetween during normal operation. A p+ region in the n-well region is connected to a second voltage supply of greater value than the first voltage supply during normal operation. Current is conducted through the n+ region to the p+ region during an electrostatic discharge event.

Abstract: In a high voltage n-channel MOS structure, inserting p+ diffusion and an n-well into NMOS drain area, along with providing ESD protection by means of forming parasitic SCR, allows using signal of 5V and decreases snapback voltage below 2V.

Abstract: This invention provides a circuit for eliminating unexpected transistor channel turn-on caused by electrostatic discharge, ESD, zapping. It provides circuits which detect ESD over-voltage conditions and which pull down the voltage to the sensitive logic devices in the input/output pre-driver circuitry during ESD zapping. There is an Input/Output control circuit which interfaces with the sense circuit, feedback circuit and with the input/output pad of the semiconductor chip to be protected from ESD damage. The purpose of this I/O circuit is to use the ESD sense circuit and an internal feedback node to pull down the voltage on the gates of the MOSFET devices most vulnerable to unexpected channel turn on during the during of the ESD over-voltage condition.

Abstract: In a high voltage n-channel MOS structure, inserting p+ diffusion and an n-well into NMOS drain area, along with providing ESD protection by means of forming parasitic SCR, allows using signal of 5V and decreases snapback voltage below 2V.

Abstract: A method is provided for forming a highly dense stacked gate flash memory cell with a structure having multi floating gates that can assume 4 states and, therefore, store 2 bits at the same time. This is accomplished by providing a semiconductor substrate having gate oxide formed thereon, and shallow trench isolation and a p-well formed therein. A layer of nitride is next formed over the substrate and an opening formed therein. Polysilicon floating gate spacers are formed in the opening. A dielectric layer is then formed over the floating gates followed by the forming of a control gate. The adjacent nitride layer is then removed leaving a multi-level structure comprising a control gate therebetween multi floating gates with the intervening dielectric layer.

Abstract: This invention provides two circuit embodiments for a whole chip electrostatic discharge, ESD, protection scheme. It also includes a method for whole chip ESD protection. This invention relates to distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths. The advantage of this invention is the ability to create a parallel discharge path to ground in order to discharge the damaging ESD current quickly so as to avoid circuit damage. The two circuit embodiments show how the protection circuits of this invention at both the unzapped I/O pads and the zapped I/O pad are connected in a parallel circuit for discharging ESD currents quickly. These protection embodiments require a small amount of semiconductor area, since the smaller protection circuits are distributed and placed at the locations of each I/O pad.

Abstract: An ESD protection circuit protects integrated circuits having multiple power supply voltage sources from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage sources. The ESD protection circuit has a string of serially connected lateral polycrystalline silicon diodes characterized by consistent turn-on threshold voltage level such that as the number of stage of the ESD protection circuit increase, the turn-on voltage threshold of the ESD protection circuit increase linearly.

Abstract: An ESD protection circuit protects integrated circuits having multiple power supply voltage sources from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage sources. The ESD protection circuit has a string of serially connected lateral polycrystalline silicon diodes characterized by consistent turn-on threshold voltage level such that as the number of stage of the ESD protection circuit increase, the turn-on voltage threshold of the ESD protection circuit increase linearly.

Abstract: CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively.

Abstract: A combination erase method to erase data from a flash EEPROM eliminates electrical charges trapped in the tunneling oxide of a flash EEPROM to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. A first embodiment method to erase a flash EEPROM cell begins by negative gate erasing to remove charges from the floating gate, followed by a source erasing to further remove charges from the floating gate, and finally followed by a channel erasing to detrap charges. A second embodiment begins with a negative gate erasing having a incremental stepping of the voltages to remove the charges from the floating gate. This followed by a source erasing to detrap the tunneling oxide of the EEPROM cell. A third embodiment begins with a source erasing having a incremental stepping of the voltages to remove the charges from the floating gate. This followed by a channel erasing to detrap the tunneling oxide of the EEPROM cell.

Abstract: A vertical transistor memory device includes FET cells formed in rows and columns with the rows orthogonally arranged relative to the columns. Several cells in a single row have a common source region and adjacent cells have a common drain region FOX regions are formed between the rows. A set of trenches are formed with sidewalls and a bottom in a semiconductor substrate with threshold implant regions formed in the sidewalls. Doped drain regions are formed near the surface of the substrate and doped source regions are formed in the base of the device below the trenches with oppositely doped channel regions therebetween. A tunnel oxide layer is formed over the substrate including the trenches aside from FOX regions. Floating gates of doped polysilicon are formed over the tunnel oxide layer in the trenches. An interelectrode dielectric layer covers the floating gate layer. Control gate electrodes of doped polysilicon are formed over the interelectrode dielectric layer.

Abstract: A silicon controlled rectifier includes a pair of complementary bipolar transistors. At least one of the pair of transistors exhibits a reach-through effect that occurs prior to the avalanche junction voltage breakdown.

Abstract: An MOS integrated circuit, such as an input-output buffer, exhibits improved resistance to damage from electrostatic discharge (ESD) by balancing the ESD current flow through active and inactive sections of drivers. Better balance of the ESD current flow is achieved by increasing the width and length of nulti-finger channels of semiconductor material defining the gates of the drivers in the active section. Wider, longer gates of the drivers in the active section increase their ability to carry current, thereby resulting in a more symmetrical distribution of ESD current between the active and inactive sections without degrading the IC's normal performance.