Abstract: A method of forming a vertical transistor memory device comprises the following process steps. Before forming the trenches, FOX regions are formed between the rows. Then form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thin floating gate layer of doped polysilicon over the tunnel oxide layer extending above the trenches. Etch the floating gate layer leaving upright floating gate strips of the floating gate layer along the sidewalls of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thin control gate layer of doped polysilicon over the interelectrode dielectric layer.

Abstract: An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors.

Abstract: The present invention provides an ESD protection component, comprising at least two MOS field effect transistors (FETs) of a first conductivity type and a first well having a first conductivity type. The two MOS FETs have two parallel gates formed on a first semiconductive layer having a second conductivity type. The first well formed on the first semiconductive layer is comprised of a connecting area formed between the MOS FETs, two parallel extension areas formed perpendicular to the gates of the MOS FETs, and a first doping area of the second conductivity type formed in the connecting area. Two SCR are formed with drains of the MOS FETs, the first semiconductive layer, the first well and the first doping region. With the combination of the SCR and NMOS FET, ESD protection efficiency can be substantially enhanced.

Abstract: CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively.

Abstract: A method of forming a vertical transistor memory device includes the following steps. Before forming the trenches, FOX regions are formed between the rows. Form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thick floating gate layer of doped polysilicon over the tunnel oxide layer filling the trenches and extending above the trenches. Etch the floating gate layer down below the top of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thick control gate layer of doped polysilicon over the interelectrode dielectric layer. Pattern the control gate layer into control gate electrodes.

Abstract: An MOS integrated circuit, such as an input-output buffer, exhibits improved resistance to damage from electrostatic discharge (ESD) by balancing the ESD current flow through active and inactive sections of drivers. Better balance of the ESD current flow is achieved by increasing the width and length of multi-finger channels of semiconductor material defining the gates of the drivers in the active section. Wider, longer gates of the drivers in the active section increase their ability to carry current, thereby resulting in a more symmetrical distribution of ESD current between the active and inactive sections without degrading the IC's normal performance.

Abstract: A vertical memory device on a silicon semiconductor substrate is formed by the following steps. Form an array of isolation silicon oxide structures on the surface of the silicon semiconductor substrate. Form a floating gate trench in the silicon semiconductor substrate between the silicon oxide structures in the array, the trench having trench sidewall surfaces. Dope the sidewalls of the floating gate trench with a threshold implant through the trench sidewall surfaces. Form a tunnel oxide layer on the trench sidewall surfaces, the tunnel oxide layer having an outer surface. Form a floating gate electrode in the trench on the outer surface of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode. Form an interelectrode dielectric layer over the top surface of the floating gate electrode. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode.

Abstract: CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively.

Abstract: A method of forming a vertical transistor memory device includes the following steps. Before forming the trenches, FOX regions are formed between the rows. Form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thick floating gate layer of doped polysilicon over the tunnel oxide layer filling the trenches and extending above the trenches. Etch the floating gate layer down below the top of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thick control gate layer of doped polysilicon over the interelectrode dielectric layer. Pattern the control gate layer into control gate electrodes.

Abstract: A method for incorporating an ion implanted channel stop layer under field isolation for a twin-well CMOS process is described in which the layer is placed directly under the completed field isolation by a blanket boron ion implant over the whole wafer. The channel stop implant follows planarization of the field oxide and is thereby essentially at the same depth in both field and active regions. Subsequently implanted p- and n-wells are formed deeper than the channel stop layer, the n-well implant being of a sufficiently higher dose to over compensate the channel stop layer, thereby removing it's effect from the n-well. A portion of the channel stop implant under the field oxide adjacent the p-well provides effective anti-punchthrough protection with only a small increase in junction capacitance. The method is shown for, and is particularly effective in, processes utilizing shallow trench isolation.

Abstract: An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors.

Abstract: A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern gate electrode stacks formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Pattern source line slots in the center of the gate electrode stacks down to the substrate. Form source regions at the base of the source lines slots. Form intermetal dielectric and control gate layers over the substrate covering the stacks. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Form self-aligned drain regions.

Abstract: An ESD protective circuit formed by n-type pull-up transistors and n-type pull-down transistors on a p-type silicon substrate for protecting an internal device circuit is disclosed. In the circuit, a n-well region having a p+ diffusion and a n+ diffusion therein being formed adjacent one drain region of one pull-up transistors, the p+ diffusion and a n+ diffusion, as well as all the drain regions of the pull-up transistors are coupled to a power supply. All the source regions of the pull-up transistors and drain regions of the pull-down transistors are connected to an I/O pad. All the source regions of the pull-down transistors including the p+ guardings are grounded. The gates of all transistors are connected to the internal device circuit so that the internal device circuit will be immunity from the ESD.

Abstract: An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors.

Abstract: A plasma damage protection cell using floating N/P/N and P/N/P structure, and a method to form the same are disclosed. Floating structures of the protection cell and the floating gates for the MOS devices are formed simultaneously on a semiconductor substrate having shallow trench isolation. The floating structures are implanted separately to form the N/P/N and P/N/P bipolar base, emitter and collector regions while the source/drain of the respective NMOS and PMOS devices are implanted with appropriate sequencing. The floating structures are connected to the substrate with appropriate polarity to provide protection at low leakage current levels and with tunable punch-through voltages.

Abstract: A method of manufacturing a on-chip temperature controller by co-implanting P-type and N-type ions into poly load resistors. The N and P type implant dose can be selected to create the desired cut-off temperature. First, a polysilicon layer 30 is formed on a first insulation layer 20. The polysilicon layer 30 is patterning to form a first poly-load resistor 30A and a second poly-load resistor 30B. The first and the second poly-load resistors are connected to a temperature sensor circuit 12. Both p-type and n-type impurity ions are implanted into the polysilicon layer 30. An insulating dielectric layer 40 is formed over the polysilicon layer 30 and the first insulating layer 20. The polysilicon layer is annealed. The contact openings 44 are formed through the ILD dielectric layer 40 exposing portions of the polysilicon layer 30. Contacts 50 to the polysilicon layer 30 thereby forming a first and second poly-load resistors which are used a temperature on-chip sensors.

Abstract: A new method of suppressing short channel effect without increasing junction leakage and capacitance using a single self-aligning delta-channel implant is described. A pad oxide layer is formed over a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer and patterned to leave an opening where a gate electrode will be formed. Dielectric spacers are formed on the sidewalls of the opening wherein a portion of the substrate is not covered by the spacers within the opening. A single delta-channel implant is made into the semiconductor substrate using the silicon nitride layer and the dielectric spacers as a mask. This delta-channel implant suppresses short channel effect without increasing junction leakage and capacitance. The dielectric spacers are removed. A polysilicon layer is deposited over the silicon nitride layer and within the opening and polished to leave the polysilicon layer only within the opening.

Abstract: A stacked-gate flash memory cell is provided having step-shaped poly-gates with increased overlap area between them in order to increase the coupling ratio and hence the program speed of the cell. The floating gate is first formed with a step and the intergate dielectric is conformally shaped thereon followed by the forming of the control gate thereon. The increase in the overlap area can be achieved by forming gates with multiply connected surfaces of different shapes.

Abstract: In short-channel MOSFET devices with gates constructed using conventional double-diffusing techniques, damage to the silicon substrate region near the gate structure causes hot carrier effects that degrade the device performance. The inventive process described minimizes damage to the silicon substrate in the region of the metal gate structure thereby providing a MOSFET device with superior hot carrier effect performance.

Abstract: A stacked-gate flash memory cell is provided having step-shaped poly-gates with increased overlap area between them in order to increase the coupling ratio and hence the program speed of the cell. The floating gate is first formed with a step and the intergate dielectric is conformally shaped thereon followed by the forming of the control gate thereon. The increase in the overlap area can be achieved by forming gates with multiply connected surfaces of different shapes.