Patents by Inventor Shuichiro Yasuda
Shuichiro Yasuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11462685Abstract: A switch device according to an embodiment of the present disclosure includes a first electrode; a second electrode opposed to the first electrode; and a switch layer including selenium (Se), at least one kind of germanium (Ge) or silicon (Si), boron (B), carbon (C), (Ga), and arsenic (As), and provided between the first electrode and the second electrode.Type: GrantFiled: January 31, 2019Date of Patent: October 4, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hiroaki Sei, Kazuhiro Ohba, Shuichiro Yasuda
-
Publication number: 20220162742Abstract: Provided are a sputtering target that makes it possible to form a chalcogenide material film with enhanced heat resistance, a method of manufacturing the sputtering target, and a memory device manufacturing method. The sputtering target includes an alloy containing a first component containing arsenic and selenium and a second component containing at least one of boron and carbon.Type: ApplicationFiled: March 13, 2020Publication date: May 26, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Kazuhiro OHBA, Shuichiro YASUDA, Hiroaki SEI, Katsuhisa ARATANI
-
Patent number: 10923658Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.Type: GrantFiled: June 13, 2019Date of Patent: February 16, 2021Assignee: Micron Technology, Inc.Inventors: Shuichiro Yasuda, Noel Rocklein, Scott E. Sills, Durai Vishak Nirmal Ramaswamy, Qian Tao
-
Publication number: 20210036221Abstract: A switching device according to an embodiment of the present disclosure includes: a first electrode; a second electrode disposed to be opposed to the first electrode; and a switching layer provided between the first electrode and the second electrode. The switching layer includes at least one chalcogen element selected from sulfur (S), selenium (Se), and tellurium (Te). At least one of the first electrode or the second electrode includes carbon (C) and, as an additive element, at least one of germanium (Ge), phosphorus (P), or arsenic (As).Type: ApplicationFiled: March 14, 2019Publication date: February 4, 2021Inventors: KAZUHIRO OHBA, HIROAKI SEI, SHUICHIRO YASUDA
-
Publication number: 20210005252Abstract: A cross point device according to an embodiment of the present disclosure includes a first electrode, a second electrode that is provided to be opposed to the first electrode, and a memory, a selector, and a resistor that are stacked between the first electrode and the second electrode. Of the resistor, a resistance value obtained through application of a negative voltage is lower than a resistance value obtained through application of a positive voltage.Type: ApplicationFiled: February 12, 2019Publication date: January 7, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Shuichiro YASUDA, Minoru IKARASHI
-
Publication number: 20200411759Abstract: A switch device according to an embodiment of the present disclosure includes a first electrode; a second electrode opposed to the first electrode; and a switch layer including selenium (Se), at least one kind of germanium (Ge) or silicon (Si), boron (B), carbon (C), (Ga), and arsenic (As), and provided between the first electrode and the second electrode.Type: ApplicationFiled: January 31, 2019Publication date: December 31, 2020Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hiroaki SEI, Kazuhiro OHBA, Shuichiro YASUDA
-
Patent number: 10658588Abstract: Memory structures with a plurality of memory cells that each include memory devices in combination with switch devices are provided. The memory device and switch device of each cell are connected in series, and include at least first and second electrodes. The first electrode features a relatively high resistance, to provide a reduced snap current during operation of the memory device. The first electrode with a relatively high resistance can contain or be entirely composed of TiAlN.Type: GrantFiled: April 6, 2017Date of Patent: May 19, 2020Assignee: Sony CorporationInventors: Shuichiro Yasuda, Tomohito Tsushima
-
Publication number: 20200066794Abstract: Memory structures with a plurality of memory cells that each include a memory device in combination with a switch device are provided. The memory device and switch device of each cell are connected in series, and include at least first and second electrodes. The first electrode features a relatively high resistance, to provide a reduced snap current during operation of the memory device. The first electrode with a relatively high resistance can contain or be entirely composed of TiAlN.Type: ApplicationFiled: March 19, 2018Publication date: February 27, 2020Applicant: SONY CORPORATIONInventors: Shuichiro YASUDA, Tomohito TSUSHIMA
-
Patent number: 10490740Abstract: A method of manufacture of a non-volatile memory system comprising: forming a dielectric layer having a hole; depositing a first electrode in the hole of the dielectric layer; applying an ion source layer over the first electrode; and depositing a second electrode over the ion source layer including: depositing an interface layer on the ion source layer, and applying a cap layer on the interface layer.Type: GrantFiled: August 9, 2013Date of Patent: November 26, 2019Assignee: Sony Semiconductor Solutions CorporationInventors: Shuichiro Yasuda, Dale Collins, Scott E. Sills
-
Publication number: 20190296235Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.Type: ApplicationFiled: June 13, 2019Publication date: September 26, 2019Applicant: Micron Technology, Inc.Inventors: Shuichiro Yasuda, Noel Rocklein, Scott E. Sills, Durai Vishal Nirmal Ramaswamy, Qian Tao
-
Patent number: 10388871Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.Type: GrantFiled: October 25, 2016Date of Patent: August 20, 2019Assignee: Micron Technology, Inc.Inventors: Shuichiro Yasuda, Noel Rocklein, Scott E. Sills, Durai Vishak Nirmal Ramaswamy, Qian Tao
-
Publication number: 20180294408Abstract: Memory structures with a plurality of memory cells that each include memory devices in combination with switch devices are provided. The memory device and switch device of each cell are connected in series, and include at least first and second electrodes. The first electrode features a relatively high resistance, to provide a reduced snap current during operation of the memory device. The first electrode with a relatively high resistance can contain or be entirely composed of TiAlN.Type: ApplicationFiled: April 6, 2017Publication date: October 11, 2018Inventors: Shuichiro Yasuda, Tomohito Tsushima
-
Publication number: 20170040534Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.Type: ApplicationFiled: October 25, 2016Publication date: February 9, 2017Applicant: Micron Technology, Inc.Inventors: Shuichiro Yasuda, Noel Rocklein, Scott E. Sills, Durai Vishak Nirmal Ramaswamy, Qian Tao
-
Patent number: 9543514Abstract: A memory component including first and second electrodes with a memory layer therebetween, the memory layer having first and second memory layers, the first memory layer containing aluminum and a chalcogen element of tellurium, the second memory layer between the first memory layer and the first electrode and containing an aluminum oxide and at least one of a transition metal oxide and a transition metal oxynitride having a lower resistance than the aluminum oxide.Type: GrantFiled: November 24, 2015Date of Patent: January 10, 2017Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Kazuhiro Ohba, Shuichiro Yasuda, Tetsuya Mizuguchi, Katsuhisa Aratani, Masayuki Shimuta, Akira Kouchiyama, Mayumi Ogasawara
-
Patent number: 9508931Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.Type: GrantFiled: December 29, 2014Date of Patent: November 29, 2016Assignee: Micron Technology, Inc.Inventors: Shuichiro Yasuda, Noel Rocklein, Scott E. Sills, Durai Vishal Nirmal Ramaswamy, Qian Tao
-
Patent number: 9444042Abstract: Some embodiments include a memory cell that has an electrode, a switching material over the electrode, a buffer region over the switching material, and an ion reservoir material over the buffer region. The buffer region includes one or more elements from Group 14 of the periodic table in combination with one or more chalcogen elements. Some embodiments include methods of forming memory cells.Type: GrantFiled: December 1, 2015Date of Patent: September 13, 2016Assignee: Micron Technology, Inc.Inventors: Christopher W. Petz, Dale W. Collins, Scott E. Sills, Shuichiro Yasuda
-
Method of making memory element with ion source layer comprised of two or more unit IO source layers
Patent number: 9356232Abstract: A method of making memory element, including: a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer containing an oxide, and the resistance change layer being provided on the first electrode side, and an ion source layer in a stacking structure of two or more of a unit ion source layer, the unit ion source layer including a first layer and a second layer, the first layer containing one or more of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and an easy-to-move element that is easy to move in the memory layer, and having a density distribution of the easy-to-move element from the first electrode to the second electrode, and the second layer containing a difficult-to-move element that is difficult to move in the memory layer.Type: GrantFiled: November 13, 2014Date of Patent: May 31, 2016Assignee: SONY CORPORATIONInventors: Kazuhiro Ohba, Tetsuya Mizuguchi, Shuichiro Yasuda, Masayuki Shimuta, Katsuhisa Aratani -
Publication number: 20160104840Abstract: A resistive memory includes a memory cell having a first electrode, a second electrode and a resistive memory element between the first electrode and the second electrode. The memory cell includes a thermally insulating region. The thermally insulating region may be included in at least one electrode of the memory cell and/or within an electrically insulating region. The thermally insulating region can confine heat within the memory cell and thereby can reduce the current and/or voltage needed to write information in the resistive memory element.Type: ApplicationFiled: October 10, 2014Publication date: April 14, 2016Inventors: Beth Cook, Nirmal Ramaswamy, Shuichiro Yasuda, Scott Sills, Koji Miyata
-
Publication number: 20160093803Abstract: Some embodiments include a memory cell that has an electrode, a switching material over the electrode, a buffer region over the switching material, and an ion reservoir material over the buffer region. The buffer region includes one or more elements from Group 14 of the periodic table in combination with one or more chalcogen elements. Some embodiments include methods of forming memory cells.Type: ApplicationFiled: December 1, 2015Publication date: March 31, 2016Applicant: Micron Technology, Inc.Inventors: Christopher W. Petz, Dale W. Collins, Scott E. Sills, Shuichiro Yasuda
-
Publication number: 20160079528Abstract: A memory component including first and second electrodes with a memory layer therebetween, the memory layer having first and second memory layers, the first memory layer containing aluminum and a chalcogen element of tellurium, the second memory layer between the first memory layer and the first electrode and containing an aluminum oxide and at least one of a transition metal oxide and a transition metal oxynitride having a lower resistance than the aluminum oxide.Type: ApplicationFiled: November 24, 2015Publication date: March 17, 2016Inventors: Kazuhiro Ohba, Shuichiro Yasuda, Tetsuya Mizuguchi, Katsuhisa Aratani, Masayuki Shimuta, Akira Kouchiyama, Mayumi Ogasawara