Patents by Inventor Shunichi Saito
Shunichi Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240118649Abstract: An image forming apparatus includes: an image carrier; a solid lubricant; a lubricant application member that scrapes off the solid lubricant and applies the scraped solid lubricant to a surface of the image carrier; a colorimeter that performs colorimetry of a colorimetric surface of the solid lubricant; and a hardware processor that sets a lubricant application condition such that a predetermined amount of lubricant is applied on the basis of a colorimetric result obtained by the colorimeter.Type: ApplicationFiled: October 3, 2023Publication date: April 11, 2024Applicant: Konica Minolta, Inc.Inventors: Hokuto HATANO, Shunichi TAKAYA, Kazuhiro SAITO
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Patent number: 11941322Abstract: Provided is a display control device including: a voice receiver configured to receive a voice utterance from a user; a communication unit configured to receive information for the voice utterance from a server via a network; and a controller configured to select an item corresponding to the voice utterance on the basis of the information that has been received, and configured to control an action in response to the item that has been selected, in which the item includes a first item in an inside of a display screen and a second item that becomes displayable by scrolling, and the controller selects either the first item or the second item on the basis of the information that has been received. The present technology is applicable to, for example, a television receiver.Type: GrantFiled: December 13, 2019Date of Patent: March 26, 2024Assignee: Saturn Licensing LLCInventors: Takuo Watanabe, Nobuhiro Ozu, Tsuyoshi Yamada, Shunichi Sugiura, Naoki Saito
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Publication number: 20240078173Abstract: A training operation may be performed by a memory controller to provide a system clock signal and a data clock signal having a desired temporal (e.g., phase) relationship to one another. The system clock and data clock signals may be provided to a memory. In some examples, the memory controller may provide a command to the memory to put the memory in a training mode. Once in the training mode, the memory controller may provide a write command and toggle the data clock signal a number of times. If the memory provides one output, the memory controller may adjust the relationship between the data clock and system clock signals. If the memory provides another output, the memory controller may maintain the relationship between the data clock and system clock signals and exit the training mode.Type: ApplicationFiled: July 17, 2023Publication date: March 7, 2024Applicant: MICRON TECHNOLOGY, INC.Inventors: OSAMU NAGASHIMA, YOSHINORI MATSUI, KEUN SOO SONG, HIROKI TAKAHASHI, SHUNICHI SAITO
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Patent number: 11914874Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.Type: GrantFiled: August 2, 2021Date of Patent: February 27, 2024Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
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Publication number: 20240038289Abstract: A clock generator circuit may generate internal data clock signals, such as quadrature phase clock signals, based at least in part, on one clock signal responsive, at least in part, to another clock signal. In some examples, the internal data clock signals may be generated from a system clock signal responsive to a data clock signal. In some examples, the internal data clock signal may be generated by sampling the system clock signal. In some examples, the sampling may be performed responsive to the data clock signal. In some examples, a latch may latch a state of the system clock signal responsive to the data clock signal. The latch may output the internal data clock signal.Type: ApplicationFiled: July 17, 2023Publication date: February 1, 2024Applicant: MICRON TECHNOLOGY, INC.Inventors: Osamu NAGASHIMA, Yoshinori MATSUI, Keun Soo SONG, Hiroki TAKAHASHI, Shunichi SAITO
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Publication number: 20230418471Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.Type: ApplicationFiled: May 31, 2023Publication date: December 28, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Dean D. Gans, Shunichi Saito
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Patent number: 11698726Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.Type: GrantFiled: December 20, 2021Date of Patent: July 11, 2023Assignee: Micron Technology, Inc.Inventors: Dean D. Gans, Shunichi Saito
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Publication number: 20220187988Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.Type: ApplicationFiled: December 20, 2021Publication date: June 16, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Dean D. Gans, Shunichi Saito
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Patent number: 11209981Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.Type: GrantFiled: September 25, 2020Date of Patent: December 28, 2021Assignee: Micron Technology, Inc.Inventors: Dean D. Gans, Shunichi Saito
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Publication number: 20210357137Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.Type: ApplicationFiled: August 2, 2021Publication date: November 18, 2021Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
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Patent number: 11150821Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.Type: GrantFiled: August 16, 2019Date of Patent: October 19, 2021Assignee: Micron Technology, Inc.Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
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Publication number: 20210149565Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks The plurality of memory banks are configured to he arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.Type: ApplicationFiled: September 25, 2020Publication date: May 20, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Dean D. Gans, Shunichi Saito
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Patent number: 11007663Abstract: A device capable of separating a remnant from a product part irrespective of a shape of the remnant. The device includes a first attraction part which attracts a first part and is moved downward; a second attraction part provided movable relative to the first attraction part to attract a second part; a jig which comes into contact with a back surface of the second part to prevent the second part from moving downward; and further a position maintaining part which maintains a position of the second attraction part relative to the first attraction part when the first attraction part is moved downward to separate the first part from the second part.Type: GrantFiled: September 18, 2015Date of Patent: May 18, 2021Assignee: Fanuc CorporationInventor: Shunichi Saito
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Patent number: 10976945Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.Type: GrantFiled: July 27, 2018Date of Patent: April 13, 2021Assignee: Micron Technology, Inc.Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
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Patent number: 10850342Abstract: A dissimilar-metal joining tool that places a ring-shaped joining auxiliary member made of iron, on a surface of a workpiece in which a second metal plate made of non-ferrous metal is laminated on a first metal plate made of iron, coaxially with a through-hole penetrates the second metal plate, and that performs arc welding toward an inner hole of the joining auxiliary member, the dissimilar-metal joining tool includes a base attached to a distal end of a robot; an arc welding torch attached to the base; a positioning mechanism provided in the base, and places the inner hole at a joining position in the arc welding torch and holds the joining auxiliary member in a radially-positioned state; and a pressing mechanism presses the joining auxiliary member in the vicinity of an outer peripheral edge.Type: GrantFiled: June 6, 2019Date of Patent: December 1, 2020Assignee: FANUC CORPORATIONInventors: Toshihiko Inoue, Shunichi Saito
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Patent number: 10788985Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.Type: GrantFiled: June 25, 2019Date of Patent: September 29, 2020Assignee: Micron Technology, Inc.Inventors: Dean D. Gans, Shunichi Saito
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Publication number: 20200009676Abstract: A dissimilar-metal joining tool that places a ring-shaped joining auxiliary member made of iron, on a surface of a workpiece in which a second metal plate made of non-ferrous metal is laminated on a first metal plate made of iron, coaxially with a through-hole penetrates the second metal plate, and that performs arc welding toward an inner hole of the joining auxiliary member, the dissimilar-metal joining tool includes a base attached to a distal end of a robot; an arc welding torch attached to the base; a positioning mechanism provided in the base, and places the inner hole at a joining position in the arc welding torch and holds the joining auxiliary member in a radially-positioned state; and a pressing mechanism presses the joining auxiliary member in the vicinity of an outer peripheral edge.Type: ApplicationFiled: June 6, 2019Publication date: January 9, 2020Applicant: FANUC CORPORATIONInventors: Toshihiko INOUE, Shunichi SAITO
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Publication number: 20200004420Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.Type: ApplicationFiled: June 25, 2019Publication date: January 2, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Dean D. Gans, Shunichi Saito
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Publication number: 20190369894Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.Type: ApplicationFiled: August 16, 2019Publication date: December 5, 2019Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
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Patent number: 10481819Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.Type: GrantFiled: October 30, 2017Date of Patent: November 19, 2019Assignee: Micron Technology, Inc.Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima