Patents by Inventor Shunichi Sukegawa

Shunichi Sukegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9972772
    Abstract: The present disclosure relates to a memory cell structure, a method of manufacturing a memory, and a memory apparatus that are capable of providing a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat. A memory cell includes: a transistor that uses a first diffusion layer formed in a bottom portion of a concave portion formed by processing a silicon substrate into a groove shape, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first diffusion layer and the second diffusion layer in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: May 15, 2018
    Assignee: Sony Corporation
    Inventors: Taku Umebayashi, Shunichi Sukegawa, Takashi Yokoyama, Masanori Hosomi, Yutaka Higo
  • Patent number: 9954024
    Abstract: The present invention relates to a semiconductor device, a solid-state image sensor and a camera system capable of reducing the influence of noise at a connection between chips without a special circuit for communication and reducing the cost as a result. The semiconductor device includes: a first chip; and a second chip, wherein the first chip and the second chip are bonded to have a stacked structure, the first chip has a high-voltage transistor circuit mounted thereon, the second chip has mounted thereon a low-voltage transistor circuit having lower breakdown voltage than the high-voltage transistor circuit, and wiring between the first chip and the second chip is connected through a via formed in the first chip.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: April 24, 2018
    Assignee: Sony Corporation
    Inventors: Shunichi Sukegawa, Noriyuki Fukushima
  • Publication number: 20180109750
    Abstract: A solid state image sensor of the present disclosure includes: a first semiconductor substrate provided with at least a pixel array unit in which pixels that perform photoelectric conversion are arranged in a matrix form; and a second semiconductor substrate provided with at least a control circuit unit that drives the pixels. The first semiconductor substrate and the second semiconductor substrate are stacked, with first surfaces on which wiring layers are formed facing each other, the pixel array unit is composed of a plurality of divided array units, the control circuit unit is provided corresponding to each of the plurality of divided array units, and electrical connection is established in each of the divided array units, through an electrode located on each of the first surfaces of the first semiconductor substrate and the second semiconductor substrate, between the pixel array unit and the control circuit unit.
    Type: Application
    Filed: December 5, 2017
    Publication date: April 19, 2018
    Applicant: Sony Corporation
    Inventors: Shunichi Sukegawa, Shunji Maeda, Junichi Ishibashi, Motoshige Okada
  • Publication number: 20180109741
    Abstract: A solid state image sensor of the present disclosure includes: a first semiconductor substrate provided with at least a pixel array unit in which pixels that perform photoelectric conversion are arranged in a matrix form; and a second semiconductor substrate provided with at least a control circuit unit that drives the pixels. The first semiconductor substrate and the second semiconductor substrate are stacked, with first surfaces on which wiring layers are formed facing each other, the pixel array unit is composed of a plurality of divided array units, the control circuit unit is provided corresponding to each of the plurality of divided array units, and electrical connection is established in each of the divided array units, through an electrode located on each of the first surfaces of the first semiconductor substrate and the second semiconductor substrate, between the pixel array unit and the control circuit unit.
    Type: Application
    Filed: February 19, 2016
    Publication date: April 19, 2018
    Applicant: Sony Corporation
    Inventors: Shunichi Sukegawa, Shunji Maeda, Junichi Ishibashi, Motoshige Okada
  • Publication number: 20180097031
    Abstract: The present invention relates to a semiconductor device, a solid-state image sensor and a camera system capable of reducing the influence of noise at a connection between chips without a special circuit for communication and reducing the cost as a result. The semiconductor device includes: a first chip; and a second chip, wherein the first chip and the second chip are bonded to have a stacked structure, the first chip has a high-voltage transistor circuit mounted thereon, the second chip has mounted thereon a low-voltage transistor circuit having lower breakdown voltage than the high-voltage transistor circuit, and wiring between the first chip and the second chip is connected through a via formed in the first chip.
    Type: Application
    Filed: December 6, 2017
    Publication date: April 5, 2018
    Inventors: Shunichi Sukegawa, Noriyuki Fukushima
  • Patent number: 9905602
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: February 27, 2018
    Assignee: Sony Corporation
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue
  • Publication number: 20170330912
    Abstract: The present invention relates to a semiconductor device, a solid-state image sensor and a camera system capable of reducing the influence of noise at a connection between chips without a special circuit for communication and reducing the cost as a result. The semiconductor device includes: a first chip; and a second chip, wherein the first chip and the second chip are bonded to have a stacked structure, the first chip has a high-voltage transistor circuit mounted thereon, the second chip has mounted thereon a low-voltage transistor circuit having lower breakdown voltage than the high-voltage transistor circuit, and wiring between the first chip and the second chip is connected through a via formed in the first chip.
    Type: Application
    Filed: August 3, 2017
    Publication date: November 16, 2017
    Inventors: Shunichi Sukegawa, Noriyuki Fukushima
  • Patent number: 9762835
    Abstract: The present invention relates to a semiconductor device, a solid-state image sensor and a camera system capable of reducing the influence of noise at a connection between chips without a special circuit for communication and reducing the cost as a result. The semiconductor device includes: a first chip; and a second chip, wherein the first chip and the second chip are bonded to have a stacked structure, the first chip has a high-voltage transistor circuit mounted thereon, the second chip has mounted thereon a low-voltage transistor circuit having lower breakdown voltage than the high-voltage transistor circuit, and wiring between the first chip and the second chip is connected through a via formed in the first chip.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: September 12, 2017
    Assignee: Sony Corporation
    Inventors: Shunichi Sukegawa, Noriyuki Fukushima
  • Publication number: 20170180668
    Abstract: The present invention relates to a semiconductor device, a solid-state image sensor and a camera system capable of reducing the influence of noise at a connection between chips without a special circuit for communication and reducing the cost as a result. The semiconductor device includes: a first chip; and a second chip, wherein the first chip and the second chip are bonded to have a stacked structure, the first chip has a high-voltage transistor circuit mounted thereon, the second chip has mounted thereon a low-voltage transistor circuit having lower breakdown voltage than the high-voltage transistor circuit, and wiring between the first chip and the second chip is connected through a via formed in the first chip.
    Type: Application
    Filed: March 3, 2017
    Publication date: June 22, 2017
    Inventors: Shunichi Sukegawa, Noriyuki Fukushima
  • Publication number: 20170141298
    Abstract: The present disclosure relates to a memory cell structure, a method of manufacturing a memory, and a memory apparatus that are capable of providing a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat. A memory cell includes: a transistor that uses a first diffusion layer formed in a bottom portion of a concave portion formed by processing a silicon substrate into a groove shape, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first diffusion layer and the second diffusion layer in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.
    Type: Application
    Filed: January 27, 2017
    Publication date: May 18, 2017
    Inventors: Taku UMEBAYASHI, Shunichi SUKEGAWA, Takashi YOKOYAMA, Masanori HOSOMI, Yutaka HIGO
  • Patent number: 9641777
    Abstract: The present invention relates to a semiconductor device, a solid-state image sensor and a camera system capable of reducing the influence of noise at a connection between chips without a special circuit for communication and reducing the cost as a result. The semiconductor device includes: a first chip 11; and a second chip 12, wherein the first chip 11 and the second chip 12 are bonded to have a stacked structure, the first chip 11 has a high-voltage transistor circuit mounted thereon, the second chip 12 has mounted thereon a low-voltage transistor circuit having lower breakdown voltage than the high-voltage transistor circuit, and wiring between the first chip and the second chip is connected through a via formed in the first chip.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: May 2, 2017
    Assignee: Sony Corporation
    Inventors: Shunichi Sukegawa, Noriyuki Fukushima
  • Patent number: 9634052
    Abstract: The present invention relates to a semiconductor device, a solid-state image sensor and a camera system capable of reducing the influence of noise at a connection between chips without a special circuit for communication and reducing the cost as a result. The semiconductor device includes: a first chip; and a second chip, wherein the first chip and the second chip are bonded to have a stacked structure, the first chip has a high-voltage transistor circuit mounted thereon, the second chip has mounted thereon a low-voltage transistor circuit having lower breakdown voltage than the high-voltage transistor circuit, and wiring between the first chip and the second chip is connected through a via formed in the first chip.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: April 25, 2017
    Assignee: Sony Corporation
    Inventors: Shunichi Sukegawa, Noriyuki Fukushima
  • Patent number: 9595562
    Abstract: A memory cell structure, a method of manufacturing a memory, and a memory apparatus that conform a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat are provided. A memory cell includes: a transistor with a first diffusion layer formed in a bottom portion of a concave portion, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first and second diffusion layers in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: March 14, 2017
    Assignee: Sony Corporation
    Inventors: Taku Umebayashi, Shunichi Sukegawa, Takashi Yokoyama, Masanori Hosomi, Yutaka Higo
  • Publication number: 20170047369
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Application
    Filed: October 26, 2016
    Publication date: February 16, 2017
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue
  • Patent number: 9565383
    Abstract: The present invention relates to a semiconductor device, a solid-state image sensor and a camera system capable of reducing the influence of noise at a connection between chips without a special circuit for communication and reducing the cost as a result. The semiconductor device includes: a first chip; and a second chip, wherein the first chip and the second chip are bonded to have a stacked structure, the first chip has a high-voltage transistor circuit mounted thereon, the second chip has mounted thereon a low-voltage transistor circuit having lower breakdown voltage than the high-voltage transistor circuit, and wiring between the first chip and the second chip is connected through a via formed in the first chip.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: February 7, 2017
    Assignee: Sony Corporation
    Inventors: Shunichi Sukegawa, Noriyuki Fukushima
  • Publication number: 20170012075
    Abstract: The present invention relates to a semiconductor device, a solid-state image sensor and a camera system capable of reducing the influence of noise at a connection between chips without a special circuit for communication and reducing the cost as a result. The semiconductor device includes: a first chip; and a second chip, wherein the first chip and the second chip are bonded to have a stacked structure, the first chip has a high-voltage transistor circuit mounted thereon, the second chip has mounted thereon a low-voltage transistor circuit having lower breakdown voltage than the high-voltage transistor circuit, and wiring between the first chip and the second chip is connected through a via formed in the first chip.
    Type: Application
    Filed: September 22, 2016
    Publication date: January 12, 2017
    Inventors: Shunichi Sukegawa, Noriyuki Fukushima
  • Patent number: 9508772
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: November 29, 2016
    Assignee: Sony Corporation
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue
  • Publication number: 20160286150
    Abstract: The present invention relates to a semiconductor device, a solid-state image sensor and a camera system capable of reducing the influence of noise at a connection between chips without a special circuit for communication and reducing the cost as a result. The semiconductor device includes: a first chip; and a second chip, wherein the first chip and the second chip are bonded to have a stacked structure, the first chip has a high-voltage transistor circuit mounted thereon, the second chip has mounted thereon a low-voltage transistor circuit having lower breakdown voltage than the high-voltage transistor circuit, and wiring between the first chip and the second chip is connected through a via formed in the first chip.
    Type: Application
    Filed: June 8, 2016
    Publication date: September 29, 2016
    Inventors: Shunichi Sukegawa, Noriyuki Fukushima
  • Publication number: 20160260774
    Abstract: A memory cell structure, a method of manufacturing a memory, and a memory apparatus that conform a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat are provided. A memory cell includes: a transistor with a first diffusion layer formed in a bottom portion of a concave portion, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first and second diffusion layers in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.
    Type: Application
    Filed: October 10, 2014
    Publication date: September 8, 2016
    Inventors: Taku UMEBAYASHI, Shunichi SUKEGAWA, Takashi YOKOYAMA, Masanori HOSOMI, Yutaka HIGO
  • Publication number: 20160133665
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Application
    Filed: January 13, 2016
    Publication date: May 12, 2016
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue