Patents by Inventor Shunsuke Inoue

Shunsuke Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5827755
    Abstract: A liquid crystal image display unit created on a substrate non-transparent to the light in the visible radiation area, characterized in that a portion beneath a liquid crystal pixel part on said substrate is removed, so that the light is made transmissive through said liquid crystal pixel part.
    Type: Grant
    Filed: August 22, 1995
    Date of Patent: October 27, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takao Yonehara, Mamoru Miyawaki, Akira Ishizaki, Junichi Hoshi, Masaru Sakamoto, Shigetoshi Sugawa, Shunsuke Inoue, Toru Koizumi, Tetsunobu Kohchi, Kiyofumi Sakaguchi, Takanori Watanabe
  • Patent number: 5815223
    Abstract: A display device including a liquid crystal held between an active matrix substrate made up by arranging thin film transistors thereon, each using polycrystalline silicon as a semiconductor layer, in one-to-one relation to intersections between a plurality of signal lines and a plurality of scan lines, and an opposite substrate opposed to the active matrix substrate, wherein the active matrix substrate includes a film having tensile stress disposed at least below or above the semiconductor layer.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: September 29, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takanori Watanabe, Mamoru Miyawaki, Shunsuke Inoue, Tetsunobu Kochi
  • Patent number: 5812231
    Abstract: A high-density impurity semiconductor region having the same conductivity type as a single-crystal silicon substrate is formed in addition to a main circuit portion of a peripheral circuit on the single-crystal silicon substrate. This semiconductor region is connected to a given potential point directly leading to an electric source. Alternatively, at a part of the peripheral drive circuit, a high-density impurity semiconductor region having a conductivity type reverse to that of the single-crystal silicon substrate is formed, and this semiconductor region is connected to a given potential point directly leading to an electric source. This can solve the problem that photocarriers (electrons and/or holes) caused by the light having not cut off and having entered into the single-crystal silicon region may enter into the peripheral drive circuit through the single-crystal silicon substrate to cause misoperation of the circuit.
    Type: Grant
    Filed: June 19, 1995
    Date of Patent: September 22, 1998
    Inventors: Tetsunobu Kochi, Mamoru Miyawaki, Shunsuke Inoue, Takanori Watanabe
  • Patent number: 5773355
    Abstract: A semiconductor substrate includes a semiconductor layer, where the density of an impurity is reduced by out diffusion, provided on an insulating layer. In a method for manufacturing such a semiconductor substrate, a semiconductor substrate including a high-density impurity layer at the side of its surface is bonded to another substrate having an insulating layer. Thereafter, the semiconductor substrate is removed, and the impurity density of the remaining high-density impurity layer is reduced by out diffusion.
    Type: Grant
    Filed: May 29, 1997
    Date of Patent: June 30, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shunsuke Inoue, Mamoru Miyawaki, Yoshihiko Fukumoto
  • Patent number: 5757054
    Abstract: The present invention solves problems as follows: a problem that, since light for displaying enters into a semiconductor substrate, carrier induced by light occurs in the semiconductor substrate, potential of the substrate fluctuates, and hence display characteristics become worse; a problem that, in the semiconductor substrate, voltages are applied to the peripheral driving circuits so as to operate the peripheral driving circuits formed in a single-crystal area, which makes display characteristics worse by the voltages being conducted to the display area through the substrate; and a problem that, in case potentials of adjacent pixels greatly differ, the difference locally changes.
    Type: Grant
    Filed: September 16, 1996
    Date of Patent: May 26, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mamoru Miyawaki, Shunsuke Inoue
  • Patent number: 5712684
    Abstract: A viewing apparatus exhibiting high performance and an image forming apparatus including the same. The viewing apparatus includes a projection optical system for projecting an image on a viewer's eye, a detector for detecting the refractive power of the viewer's eye, and an adjustor for adjusting the projection optical system so that the image is formed substantially on a viewer's eye fundus. The imaging apparatus includes an imager for forming an image of an object, a projection optical system for projecting the object image on the viewer's eye, a detector for detecting the refractive power of the viewer's eye, and an adjustor for adjusting the projection optical system so that the object image is formed substantially on the viewer's eye fundus in accordance with the refractive power of the viewer's eye.
    Type: Grant
    Filed: April 3, 1996
    Date of Patent: January 27, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shunsuke Inoue, Hidekazu Takahashi
  • Patent number: 5700719
    Abstract: A semiconductor device, wherein an electrode wiring, which is in contact with semiconductor layers of mutually different conductive types and serves to connect at least he layers of mutually different conductive types, comprises a first portion principally composed of a component same as the principal component of the semiconductor layers, and a second portion consisting of a metal.
    Type: Grant
    Filed: March 30, 1995
    Date of Patent: December 23, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroshi Yuzurihara, Shunsuke Inoue, Mamoru Miyawaki, Shigeyuki Matsumoto
  • Patent number: 5693959
    Abstract: A thin film transistor comprises a source region, a drain region and a channel region formed in a thin film silicon region on an insulating substrate and a gate electrode formed via a gate insulating film on the channel region; at least one of the source region and the drain region has a high-concentration impurity region and a low-concentration impurity region; the channel region is in contact with the low-concentration impurity region; the low-concentration impurity region comprises at least a first region and a second region; the first region comprises a thin film having about the same thickness as the channel region; the second region comprises a thin film having about the same thickness as the high-concentration impurity region which is thicker than the first region. A liquid crystal display has TFT substrates wherein the thin film transistors are arranged in the form of a matrix.
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: December 2, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shunsuke Inoue, Takeshi Ichikawa
  • Patent number: 5691794
    Abstract: A liquid crystal display device comprised of picture element electrodes provided on a first plane of a substrate and an opposed electrode placed opposedly to the picture element electrodes, between which a liquid crystal is carried, characterized in that in a region of the substrate corresponding to the picture element electrodes is formed a concave portion from the second plane opposite the first plane of the substrate, the region being light translucent, and the concave portion having a translucent material enclosed therein.
    Type: Grant
    Filed: January 31, 1994
    Date of Patent: November 25, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Junichi Hoshi, Shigetoshi Sugawa, Shunsuke Inoue, Osamu Hamamoto, Yoshihiko Fukumoto, Yutaka Genchi, Masaru Kamio, Mamoru Miyawaki
  • Patent number: 5614439
    Abstract: A semiconductor device with a high-density wiring structure, and a producing method for such device are provided. The semiconductor device has a substrate such as silicon, an insulation layer laminated on the substrate and having a groove or a hole, and a wiring of a conductive material formed in the groove or hole in the insulation layer. The wiring is formed by depositing a conductive material such as aluminum or an aluminum alloy in the groove or hole of the insulation layer by a CVD method utilizing alkylaluminum hydride gas and hydrogen. The groove or hole can be formed by an ordinary patterning method combined with etching.
    Type: Grant
    Filed: February 21, 1995
    Date of Patent: March 25, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Fumio Murooka, Tetsuo Asaba, Shigeyuki Matsumoto, Osamu Ikeda, Toshihiko Ichise, Yukihiko Sakashita, Shunsuke Inoue
  • Patent number: 5599741
    Abstract: A semiconductor device including a field effect transistor has source and drain areas formed on the main surface of a semiconductor substrate and a gate electrode formed on the main surface across a gate insulation film. The gate electrode has a first electrode portion with an electron donating surface and a second electrode portion consisting of metal formed on the first electrode portion.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: February 4, 1997
    Assignee: Cannon Kabushiki Kaisha
    Inventors: Shigeyuki Matsumoto, Hiroshi Yuzurihara, Mamoru Miyawaki, Shunsuke Inoue, Jun Nakayama
  • Patent number: 5598037
    Abstract: A semiconductor device including: an insulated gate type transistor having a columnar semiconductor region formed on the main side of a semiconductor substrate, a gate electrode formed on the side surface of the columnar semiconductor region while interposing a gate insulating film and main electrode regions respectively formed on and formed below the columnar semiconductor region; and a memory element which is formed on the upper main electrode region and which can be broken electrically.
    Type: Grant
    Filed: March 15, 1995
    Date of Patent: January 28, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shin Kikuchi, Mamoru Miyawaki, Genzo Monma, Hayao Ohzu, Shunsuke Inoue, Yoshio Nakamura, Takeshi Ichikawa, Osamu Ikeda, Tetsunobu Kohchi
  • Patent number: 5541454
    Abstract: A semiconductor device comprises a capacitor consisting of an Al region formed on a semiconductor substrate, an Al oxide film formed on a surface of said Al region, and electrodes opposed to said Al region with interposition of said Al oxide film.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 30, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shunsuke Inoue, Yukihiko Sakashita, Yoshio Nakamura, Shin Kikuchi, Hiroshi Yuzurihara
  • Patent number: 5536361
    Abstract: A process for preparing a semiconductor substrate comprises a step of making a silicon substrate porous, a step of forming a non-porous silicon monocrystalline layer on the resulting porous substrate, a step of bonding the surface of the non-porous silicon monocrystalline layer to another substrate having a metallic surface, and a step of removing the porous silicon layer of the bonded substrates by selective etching.
    Type: Grant
    Filed: January 23, 1995
    Date of Patent: July 16, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shigeki Kondo, Shigeyuki Matsumoto, Akira Ishizaki, Shunsuke Inoue, Yoshio Nakamura
  • Patent number: 5530266
    Abstract: A liquid crystal image display unit created on a substrate non-transparent to the light in the visible radiation area, characterized in that a portion beneath a liquid crystal pixel part on said substrate is removed, so that the light is made transmissive through said liquid crystal pixel part.
    Type: Grant
    Filed: May 13, 1994
    Date of Patent: June 25, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takao Yonehara, Mamoru Miyawaki, Akira Ishizaki, Junichi Hoshi, Masaru Sakamoto, Shigetoshi Sugawa, Shunsuke Inoue, Toru Koizumi, Tetsunobu Kohchi, Kiyofumi Sakaguchi, Takanori Watanabe
  • Patent number: 5468344
    Abstract: The present invention is directed to a method for manufacturing semiconductor devices including a process of etching a member for use in making a semiconductor device. An improvement resides in a process for holding the member, using holding means which is placed into contact with the peripheries of the member, as well as forming a space including one face of the member, and a process for introducing a gas into the space, and blasting the gas from a clearance between the member and the holding means, as well as injecting an etching agent to the member from the opposite face side of the member to etch the other face of the member.
    Type: Grant
    Filed: January 26, 1994
    Date of Patent: November 21, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shunsuke Inoue, Junichi Hoshi, Takanori Watanabe
  • Patent number: 5466961
    Abstract: A semiconductor device including: an insulated gate type transistor having a columnar semiconductor region formed on the main side of a semiconductor substrate, a gate electrode formed on the side surface of the columnar semiconductor region while interposing a gate insulating film and main electrode regions respectively formed on and formed below the columnar semiconductor region; and a memory element which is formed on the upper main electrode region and which can be broken electrically.
    Type: Grant
    Filed: April 22, 1992
    Date of Patent: November 14, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shin Kikuchi, Mamoru Miyawaki, Genzo Monma, Hayao Ohzu, Shunsuke Inoue, Yoshio Nakamura, Takeshi Ichikawa, Osamu Ikeda, Tetsunobu Kohchi
  • Patent number: 5434441
    Abstract: A semiconductor device has an NMOS transistor and a PMOS transistor formed on at least one monocrystal Si region formed in a thin-film Si layer formed on an insulation layer. The thickness T.sub.BOX of the insulation layer on which the NMOS and PMOS transistors are formed, the voltage V.sub.SS of a low-voltage power supply and the voltage V.sub.DD of a high-voltage power supply for the NMOS and PMOS transistors satisfy a relationship expressed by the following inequality:T.sub.BOX >(V.sub.DD -V.sub.SS -K.sub.2)/K.sub.1where K.sub.1 .tbd..epsilon..sub.BOX.sup.-1 (Q.sub.BN +Q.sub.BP), K.sub.2 .tbd..phi..sub.FN +.phi..sub.FP, .epsilon..sub.BOX is the dielectric constant of the base insulation layer, Q.sub.BN and Q.sub.BP are bulk charges when the widths of depletion layers of the NMOS and PMOS transistors are maximized, and .phi..sub.FN and .phi..sub.FP are pseudo Fermi potentials of the NMOS and PMOS transistors.
    Type: Grant
    Filed: August 4, 1994
    Date of Patent: July 18, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shunsuke Inoue, Toru Koizuki, Mamoru Miyawaki, Shigetoshi Sugawa
  • Patent number: 5412240
    Abstract: A semiconductor device has an NMOS transistor and a PMOS transistor formed on at least one monocrystal Si region formed in a thin-film Si layer formed on an insulation layer. The thickness T.sub.BOX of the insulation layer on which the NMOS and PMOS transistors are formed, the voltage V.sub.SS of a low-voltage power supply and the voltage V.sub.DD of a high-voltage power supply for the NMOS and PMOS transistors satisfy a relationship expressed by the following equation:T.sub.BOX >(V.sub.DD -V.sub.SS -K.sub.2)/K.sub.1where K.sub.1 .tbd..epsilon..sub.BOX (Q.sub.BN +Q.sub.BP), K.sub.2 .tbd.2.PHI..sub.FN +2.PHI..sub.FP -1.03, .epsilon..sub.BOX.sup.-1 is the dielectric constant of the base insulation layer, Q.sub.BN and Q.sub.BP are bulk charges when the widths of depletion layers of the NMOS and PMOS transistors are maximized, and .PHI..sub.FN and .PHI..sub.FP are pseudo Fermi potentials of the NMOS and PMOS transistors.
    Type: Grant
    Filed: July 14, 1994
    Date of Patent: May 2, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shunsuke Inoue, Toru Koizumi, Mamoru Miyawaki, Shigetoshi Sugawa
  • Patent number: 5218232
    Abstract: A semiconductor device, wherein an electrode wiring, which is in contact with semiconductor layers of mutually different conductive types and serves to connect at least the layers of mutually different conductive types, comprises a first portion principally composed of the same component as the principal component of the semiconductor layers, and a second portion consisting of a metal.
    Type: Grant
    Filed: May 24, 1991
    Date of Patent: June 8, 1993
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroshi Yuzurihara, Shunsuke Inoue, Mamoru Miyawaki, Shigeyuki Matsumoto