Abstract: A MOSFET includes a gate oxide formed on a substrate. A thin dielectric layer is formed on the side walls of the gate. A gate is formed on the gate oxide. A first metal silicide layer is formed on top of the gate to increase the conductivity of the gate. Spacers are formed on the substrate and are separated with the gate by a space. Air gaps are formed between the gate and the spacers. First doped ion regions are formed aligned to the air gaps in the substrate, under a portion of the dielectric layer. Second doped ion regions are formed under the spacers in the substrate, next to the first doped ion regions. Third doped ion regions are formed in the substrate next to the second doped ion regions. The third doped ion regions have relatively highly doped ions to the first doped ion regions. The second doped ion regions are formed with immediately highly doped ions between the first and the third doped ion regions.

Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. An anti-reflection layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer of the first silicon layer and of the anti-reflection layer. A portion of the gate insulator layer is removed to have undercut spaces under the first silicon layer. A dielectric layer is then formed on the semiconductor substrate, on the sidewalls of the gate region, and within the undercut spaces. A spacer structure containing first type dopants is then formed on the sidewalls of the gate region. Following the removal of the anti-reflection layer, a second silicon layer containing second type dopants is formed over the semiconductor substrate and the first silicon layer.

Abstract: The method of forming MOS transistors includes the following steps. First, isolation regions are formed in the semiconductor substrate to separate the semiconductor substrate into an ESD protective region and a functional region. A gate insulator layer is formed on the substrate and a polysilicon layer is formed on the gate insulator layer. The polysilicon layer is then patterned to form gate structures on the ESD protective region and the functional region. The semiconductor substrate is doped for forming a first doped region and an insulator layer is formed over the semiconductor substrate. A portion of the insulator layer and a portion of the gate insulator layer are removed to form spacer structures and an insulator block. The semiconductor substrate is doped for forming a second doped region. An insulator opening is defined within the insulator block. The semiconductor substrate is then doped for forming a third doped region.

Abstract: The present invention proposes a method for fabricating shallow trench regions for isolation. An oxide hard mask is utilized for the silicon etching. A silicon oxynitride film is created near the trench corners to prevent the gate wrap-around and corner parasitic leakage. Forming trench regions on a semiconductor substrate by using a thick pad oxide layer as an etching hard mask. A thermal oxide film is grown to recover the etching damages. An undoped LPCVD amorphous silicon film is then deposited on entire surface of the semiconductor substrate. A high temperature/pressure oxidation process follows to convert the undoped amorphous silicon film into thermal oxide. A thick CVD oxide layer is deposited on the semiconductor substrate. The oxide film outside the trench regions is removed by using a CMP process. Finally, the MOS devices are fabricated on the semiconductor substrate by standard processes, and thus complete the present invention.

Abstract: A method for forming a fork-shaped capacitor of a dynamic random access memory cell is disclosed. The method includes forming a first conductive layer (118) over a semiconductor substrate (110), wherein at least a portion of the first doped polysilicon layer communicates to the substrate. A first dielectric layer is formed on the first conductive layer and is then patterned to form an opening therein and expose a portion of the first conductive layer. A second conductive layer is formed on the sidewall of the first dielectric layer and the exposed portion of the first conductive layer. A second dielectric spacer is formed on the sidewall of the second conductive layer. The first conductive layer is etched using the second dielectric layer as a mask, and a third conductive spacer is formed on the sidewalls of the second dielectric spacer. The second dielectric layer are then removed.

Abstract: The present invention discloses a method of forming CMOS transistors with self-aligned planarization twin-well by using fewer mask counts. After a silicon nitride layer is formed over a pad oxide layer on a semiconductor substrate, an n-well region is defined by implanting a high energy dose phosphorous in the semiconductor substrate. When the photoresist layer used for defining the n-well is stripped, a high energy and low dose blanket boron is implanted under the n-well region in the semiconductor substrate. Next, both the silicon nitride layer and the pad oxide layer are removed. A high temperature steam oxidation process is then performed to remove the crystalline defects, and the in-situ high temperature long time anneal is done to form a deep twin-well. A thick pad oxide layer formed by the high temperature steam oxidation is then removed, and an active region is defined followed by a standard oxidation process to grow a thick field oxide region.

Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. An anti-reflection layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, of the first silicon layer, and of the anti-reflection layer. A doping step using low energy implantation or plasma immersion is carried out to dope the substrate to form an extended sourcedrain junction in the substrate under a region uncovered by the gate region. An undoped spacer structure is formed on sidewalls of the gate region and the anti-reflection layer is then removed. A second silicon layer is formed on the semiconductor substrate and the first silicon layer. Another doping step is performed to dope the substrate to form a source/drain junction in the substrate under a region uncovered by the gate region and the undoped spacer structure.

Abstract: A method of fabricating buried bit line flash EEROM with shallow trench floating gate for suppressing the short channel effect is disclosed. The method comprises following steps. Firstly, a pad oxide layer and a conductive impurity (such as phosphorus) doped polysilicon layer is successively formed on the silicon substrate. Then, an oxidation process is performed to oxidize the polysilicon layer and to drive in the conductive impurities. After coating a patterned mask on the resultant surface to define a plurality of buried bit line regions, a dry etch is used to etch away the unmask regions till the silicon substrate is slightly recessed to form shallow trenches. Subsequently, the photoresist is stripped, and a gate dielectric layer, such as gate nitride or oxynitride layer is formed on the resultant surface.

Abstract: A method for forming mask read-only memories comprises: A gate oxide layer is formed on a semiconductor substrate. A polysilicon layer is formed on the gate oxide layer. Then, a silicon nitride layer is formed on said polysilicon layer. The gate structures are defined by patterning the silicon nitride layer and the polysilicon layer. Subsequently, the silicon oxide spacers are formed on the sidewalls of the gate structures. An ion implantation is performed to form the buried bit lines in said semiconductor substrate between said gate structures. A BPSG layer is formed on said semiconductor substrate. Then, the BPSG layer is polished until the top surface of said gate structures and the silicon nitride layer is removed. A conductive layer is formed along the surfaces of said residual BPSG layer, silicon oxide spacers and polysilicon layer.

Abstract: The trench isolation structure in the present invention is as follows. A lower-half trench is in the substrate. An upper-half trench in the substrate is located above the lower-half trench and the upper-half trench has a larger width than the lower-half trench. A first insulating layer is right above the lower-half trench and the upper-half trench. A second insulating layer is located over the first insulating layer. A semiconductor layer is within the lower-half trench over a portion of the second insulating layer. A third insulating layer is located on the second insulating layer and the semiconductor layer and is located within the upper-half trench. The planarized deep-shallow trench isolation in the present invention can be employed for isolating CMOS and bipolar devices. A higher packing density than conventional trench isolation is provided.

Abstract: The present invention includes forming nitrogen-doped amorphous silicon layer on the gate structure and on a pad oxide. Nitride spacers are formed on the side walls of the gate structure. Then, the nitride spacers and the cap nitride are both removed by wet etching. Next, an ion implantation is carried out to dope dopants into the gate and in the N well. Doped regions for the NMOS device are next formed in the P well by performing a further ion implantation. An oxidation is performed to convert the nitrogen-doped amorphous silicon layer to a nitrogen-doped oxide layer. An ultra-shallow source and drain junctions and the extended source and drain are obtained by using the amorphous silicon layer as a diffusion source. Next, nitrogen spacers on the side walls of the oxide are formed. The oxide on the top of the gate and uncovered by the spacers are removed during the etching to form spacers. Self-aligned silicide (SALICIDE) and polycide are respectively formed on the exposed substrate and gate.

Abstract: The present invention is a method of fabricating void-free and volcano-free tungsten plugs. A silicon film was formed over contact hole surfaces for restricting the reflow of a dielectric layer. A titanium film is formed over the silicon layer. By performing a thermal process to the silicon layer and the titanium layer in a nitride-containing environment, the etching damage to the substrate can be recovered and a silicon silicide and a titanium nitride can be formed. The contact resistance of plugs can be significantly reduced, when compared with known technology. The undesired formation of voids and volcano can be eliminated. The method can be employed to fabricate defect-free advanced ULSI devices.

Abstract: The capacitor includes a first storage node formed over a semiconductor wafer. The first storage node has a plurality of mushroom-shape structures. The plurality of mushroom-shape structures are randomly arranged on the first storage node to increase the area of the first storage node. A dielectric layer conformally covers the first storage node. A second storage node is formed on the dielectric layer.

Abstract: The structure of flash EEPROM is formed on a composite substrate, wherein said composite substrate comprises: a pad oxide layer formed on a semiconductor substrate; an n-type doped dielectric layer is formed on the pad oxide layer. A nitride layer is formed on the n-type doped oxide layer. The composite substrate has a trench. An oxynitride layer which serves as coupling oxide layer is formed on surfaces of sidewalls and bottom of portion of the semiconductor substrate of the trench. The trench is filled with an n-type conductive doped polysilicon layer. The n-type conductive doped polysilicon layer serves as a floating gate of EEPROM. A conductive layer, a semiconductor substrate layer doped by using aforementioned n-type dopant containing oxide as a diffusion source, serves as buried bit lines being formed in the semiconductor substrate and abutting the pad oxide layer. An ONO layer is formed on the polysilicon layer and the nitride layer.

Abstract: A method to fabricate double poly gate high-density multi-state flat mask ROM cells on a silcon substrate is disclosed. The method comprises the following steps. Firstly, an in-situ n+ first polysilicon/pad oxide layer is deposited on the silicon substrate, and then an ARC layer such as nitride layer is deposited to improve the resolution during the lithography process for pateterning a first formed word line. After forming a plurality of dual nitride spacers on sidewalls of the first patterned gate, a first photoresist coating on all resultant surfaces except the two predetermined regins, a first boron or BF.sub.2.sup.+ coding implant into the silicon substrate is carried out. The photoresist is then stripped and an oxidaiton process conducted in O.sub.2 ambient to grow oxide layers on all surfaces of the silicon substrate using the nitride layer as a hard mask.

Abstract: The present invention discloses an isolation method for fabricating isolation regions with less bird's peak sizes in semiconductor devices. A first pad oxide layer and a silicon nitride layer are first formed on a wafer substrate. After an undercut process is performed to the first pad oxide layer and forms a cave under the silicon nitride layer, a second pad oxide layer is formed over the wafer substrate. Next, a polysilicon layer is then deposited along the profile described above. Then, an anisotropic process is used to form sidewall spacers by etching the polysilicon layer. A recessed structure is then formed to the wafer substrate by a semi-isotropic process, and follows a thermal oxidation to fabricate isolation regions composed of silicon dioxide on the surface of the wafer substrate. The silicon nitride layer and the first pad oxide layer are then removed for continuing the active region processes.

Abstract: The method of forming buried contacts on a semiconductor substrate is as follows. At first, a gate insulator layer is formed on the substrate. An undoped silicon layer is then formed on the substrate, and a dielectric layer is formed on the undoped silicon layer. Portions of the dielectric layer, of the undoped silicon layer, and of the gate insulator layer are removed to define a buried contact opening. A doping step is carried out to dope the substrate for forming a buried contact region. A doped silicon layer is formed over the substrate. Next, a portion of the doped silicon layer is then removed to leave a silicon connection and a doped silicon sidewall. The dielectric layer is removed and a thermal oxidization is performed to form a thermal oxide layer on the exposed silicon surfaces. A gate region is defined by removing portions of the thermal oxide layer and the undoped silicon layer. The substrate is doped for forming a lightly doped source/drain region.

Abstract: The present invention includes performing a blanket ion implantation to form lightly doped drain regions (LDD) adjacent to gate structures. A second ion implantation is performed with tilted angle to form p channel punchthrough stopping regions. A third ion implantation is used to implant ions into a NMOS device region. Oxide spacers are then formed on gate structures. Next, a forth ion implantation is then carried out to dope ions into the substrate to form source and drain regions in the NMOS region and a NMOS cell region, respectively. Next, a fifth ion implantation is used to dope dopant into a PMOS device region, thereby forming source and drain regions in the PMOS device region. Subsequently, a high temperature thermal anneal is performed to form shallow junction of the devices.

Abstract: A method of fabricating a lightly doped drain transistor having an inverse-T gate structure. A semiconductor substrate is provided to implement said method. After a gate dielectric layer is formed on the substrate, the step of sequentially forming a first amorphous silicon layer and a second amorphous silicon layer follows. Then, the second amorphous silicon layer is patterned to form a first electrode, and first spacers are formed on sidewalls of the first electrode. Lightly-doped layers are thereafter formed in the substrate, and thus the first amorphous silicon layer is patterned to form a second electrode. Both steps make use of the first electrode and the first spacers as masking. Subsequently, second spacers are formed to overlie the first spacers and sidewalls of the second electrode. After heavily-doped layers are formed in the substrate by using the first electrode and the second spacers as masking, the lightly-doped layers are driven in so as to be fully covered by the second electrode.

Abstract: The present invention proposes a structure of nonvolatile memory cell with a textured tunnel oxide and a high capacitive-coupling ratio. A non-tunnel oxide is formed on the semiconductor substrate. The tunnel oxides with textured surfaces are formed on the semiconductor substrate and are separated by the non-tunnel oxide. The source and drain are formed aligned to the tunnel oxides in the semiconductor substrate. The floating gate, the interpoly dielectric and the control gate, are formed in turn over the tunnel and non-tunnel oxides. Due to the textured structure of the tunnel oxide, the high-density and high-speed nonvolatile memory can be achieved.