Abstract: The present invention proposes a method for forming vertically modulated wells in a semiconductor substrate. The method can include the steps as follows. At first, isolation regions are formed over the substrate. A pad layer is then formed over the substrate and a photoresist layer is formed over the pad layer. Then, p-well regions are defined by removing portions of the photoresist layer. Next, first p-wells are formed in the substrate under the p-well regions. After forming a masking layer over the p-well regions, the photoresist layer is removed. A first thermal process is then performed. Second p-wells are formed in the substrate at a level below the first p-wells. Next, n-wells are formed in the substrate under regions uncovered by the masking layer and above the second p-wells. The masking layer and the pad layer are then removed. Finally, a second thermal process is performed to finish the formation of vertically modulated wells.

Abstract: A buried contact structure on a semiconductor substrate in the present invention is as follows. A gate insulator is on a portion of the substrate and a gate electrode is located over the gate insulator. A gate sidewall structure is on the sidewall of the gate electrode. A lightly doped junction region in the substrate is under the gate sidewall structure. A doped junction region is in the substrate abutting the lightly doped junction region and is located aside from the gate insulator. A doped buried contact region is in the substrate next to the doped junction region. An interconnect is located over a first portion of the doped buried contact region.The buried contact structure can further include a shielding layer over a second portion of the doped buried contact region. For forming more connections, the buried contact structure can further have a dielectric layer over the interconnect, the substrate, the gate sidewall structure, and the gate electrode.

Abstract: A MOSFET with buried contacts and air-gap gate structure is disclosed. The MOSFET comprises trench isolation regions on a silicon substrate. A poly gate on the active region is formed of a gate dielectric layer and a polysilicon layer, wherein the polysilicon layer is in the midst of a portion of the gate dielectric layer so that there are two unoccupied gate dielectric regions at two sides of polysilicon layer. A first buried contact and second buried contacts are doped polysilicon layer being with respective vertical portions back to back adjacent two terminals of the gate dielectric layer and with respect horizontal portions extended to the trench isolation regions. A CVD oxide layer is formed atop the first buried contact, the poly gate, and the second buried contact to form the air gaps therein. The source/drain regions are underneath the first and second buried contacts, respectively.

Abstract: A method for fabricating simultaneously a self-aligned silicided and an ESD protective transistor is disclosed. To improve operation speed, the MOS transistor is manufactured with an extended S/D junction; however, there is no salicide and LDD and, with a normal junction in the ESD protective transistor. The method comprises the steps of: thermally grown oxide layers on a defined source/drain region and a poly-Si surface of the gate structure, Then, a photoresist is masked on the functional device, and n-type ions are implanted to form a source/drain region in the ESD protection device. Then the photoresist is removed so as to form a nitride layer on all exposed surfaces of the substrate. An anisotropic etching back the nitride layer to form spacers on sidewalls of the gate structure in the functional device by using a photoresist on the ESD protective device is followed.

Abstract: The present invention discloses a structure for 3-D transistors with high electrostatic discharge (ESD) reliability. The 3-D transistors are fabricated on a substrate. The substrate has several recess portions and silicon islands. Several buried oxide regions are formed in the silicon islands and upper portions of the silicon islands are isolated from the substrate by the buried oxide regions. Then, a gate oxide layer is formed on the substrate. The upper portions of the silicon islands are enclosed by the gate oxide layer and the buried oxide region. A gate structure is defined on each of the recess portions and silicon islands. Two N-type source/drain regions are defined in each of the silicon islands adjacent to each of the gates on the silicon islands. Two P-type source/draid regions are fabricated in each of the recess portions adjacent to each of the gates on the recess portion. Spacers are defined on the sidewalls of the gates and abutting to the gates.

Abstract: The present invention includes forming field oxide (FOX) isolations on a substrate. A pad oxide layer is then formed on the substrate. An ion implantation is carried out to dope dopants into the substrate by using FOX as a hard mask. Thus, a buried oxygen amorphized region is formed in the substrate. Subsequently, a high temperature thermal anneal is performed to convert the oxygen amorphized region into an buried oxide layer, thereby forming localized Si islands between the substrate and the buried oxide layer. A further thermal oxidation is used to narrow the thickness of the localized Si islands, thereby forming nanometer Si wires. Then, a further ultra thin gate oxide layer is regrow on the nanometer Si wires. Then, CMOS transistors are formed on the substrate.

Abstract: The method of the present invention includes patterning a gate structure. Then, a polyoxide layer is formed on side walls of the gate structure. Then, silicon nitride side wall spacers are formed on the side walls of the gate structure. Then, source/drain structure of the device is fabricated. Next, the side wall spacers are removed to expose a portion of the source and drain. Then, an undoped amorphous silicon layer is formed on the surface of the gate structure, the oxide layer and the exposed source and drain. A dry oxidation process is used to convert the amorphous silicon layer into textured tunnel oxide at the interface of the substrate and the oxide. The oxide is then removed, and a further oxide is re-deposited on the gate and substrate. Polysilicon side wall spacers are then formed. A further polysilicon layer is subsequently deposited over the gate. Then, the polysilicon layer is patterned to define the floating gate. A dielectric is formed at the top of the floating gate.

Abstract: A doped oxide and an undoped oxide are formed on a substrate. Then, the substrate is annealed to re-flow the doped oxide layer. The doped oxide is then etched back. Next, a contact hole is created by etching. An amorphous silicon layer is formed on the surface of the doped oxide layer and along the surface of the contact hole. Next, high temperature is used to recover the etching damage and simultaneously transform or convert the amorphous silicon into a polysilicon layer. A titanium layer and a titanium nitride are respectively formed onto the polysilicon layer. Next, rapid thermal process (RTP) is introduced to form a titanium silicide beneath the titanium nitride layer. A tungsten layer is formed on the titanium nitride layer and refilled into the contact hole. The tungsten layer is then etched back to form a tungsten plug with void-free in the contact hole. A conductive layer is formed on the titanium nitride layer.

Abstract: The present invention provides a method of forming buried contacts on a semiconductor substrate. The steps are as follows. At first, a gate insulator layer is formed over the substrate. A first silicon layer is then formed over the gate insulator layer. A buried contact opening is defined through the first silicon layer and the gate insulator layer extending down to the substrate. The substrate is then doped with a region under the buried contact opening for forming a buried contact region. A second silicon layer is formed over the substrate and the first silicon layer. A portion of the second silicon layer is then removed to define a gate region and an interconnect. Next, the substrate is doped for forming a second doping region under a region uncovered by the gate region and the interconnect. A thermal oxidation process is performed to oxidize an exposed portion of the first silicon layer and a portion of the second silicon layer at a top surface.

Abstract: The method for forming flash memory includes the following steps. At first, a semiconductor substrate with an isolation region formed thereupon is provided. The semiconductor substrate has a pad oxide layer and a first nitride layer formed thereover. A portion of the first nitride layer and a portion of the pad oxide layer are removed to define a gate region. A first oxide layer is formed and then a sidewall structure is formed. The semiconductor substrate is doped with first type dopants. A first thermal process is performed to form a second oxide layer and to drive in the first type dopants. The sidewall structure and the first nitride layer are then removed, and a first conductive layer is then formed over the substrate. A doping process is performed to dope the pad oxide layer, the first oxide layer, and the second oxide layer by implanting second type dopants through the first conductive layer.

Abstract: The method includes forming a buried oxide layer in a substrate. A pad oxide layer is then formed on the substrate. A silicon nitride layer is pattered on the surface of the pad oxide. Then, a thick field oxide (FOX) is formed on the pad oxide layer. Sidewall spacers are formed on the side walls of the opening of the silicon nitride layer. Next, the FOX is etched. An ion implantation is performed for adjusting the threshold voltage and anti-punch-through implantation. Subsequently, a dielectric with high permittivity is deposited along the surface of the substrate. The dielectric layer may be formed by a nitride technique. A conductive layer composed of metal or alloy is then formed on the dielectric layer and refilled into the opening. A chemical mechanical polishing is used to remove the dielectric layer, silicon nitride and the spacers such that the conductive layer remains only in the opening. The residual nitride and spacers are removed by hot phosphor acid solution. Source and drain are next created.

Abstract: The present invention includes NMOS devices on a NMOS device area and coded NMOS devices on a cell area. Isolation structures are formed between the NMOS devices and between the coded NMOS devices. N conductive type bit lines are formed under first isolation structures. A coding region is formed on the cell area between two coded NMOS devices and under a second isolation structure. Spacers are formed on the side walls of the NMOS devices and the coded NMOS devices and an anti-reflective coating layer is formed on the NMOS devices and the coded NMOS devices.

Abstract: The present invention is a method of manufacturing a high density capacitors for use in semiconductor memories. High etching selectivity between BPSG (borophososilicate glass) and CVD-oxide (chemical vapor deposition oxide) is used to fabricate a multiple fin-shape capacitor with a plurality of horizontal fins and vertical pillars. First, a contact hole formed on a semiconductor substrate using an etching process. A first polysilicon layer is then deposited in the contact hole to form a plug. A composition layer consists of BPSG and silicon oxide formed on the substrate. Then a opening is formed in the composition layer to serve as a storage node. A highly selective etching is then used to etch the BPSG sublayers of the composition layer. Next, a second polysilicon layer is formed along the surface of the composition layer, the substrate and the plug. Then a SOG layer is formed along the surface of the second polysilicon layer.

Abstract: A double-crown rugged polysilicon capacitor of a dynamic random access memory cell is formed. A second dielectric layer is formed on a first dielectric layer, followed by the formation of a first conductive layer on the second dielectric layer. Portions of the first conductive layer and the second dielectric layer are removed to define an opening. A second conductive layer is formed within the opening and on the first conductive layer. A sidewall structure is formed within the opening on sidewalls of the second conductive layer. Next, a removing step is performed to remove a portion of the second conductive layer which is uncovered by the sidewall structure. The sidewall structure and a portion of the first dielectric layer are removed, using the residual second conductive layer as a mask, to define a contact hole within the first dielectric layer. A third conductive layer fills up the contact hole.

Abstract: A method for forming a trench capacitor of a dynamic random access memory cell is disclosed. The method includes patterning to etch a semiconductor substrate (10) of a first conductivity to form a trench (18) in the substrate. Ions of the first conductivity are tilt-implanted over the trench, so that sidewalls and a bottom surface of the substrate near the trench are doped with the ions of the first conductivity. Next, first ions of a second conductivity are tilt-implanted over the trench at a first angle, thereby forming a first implanted region (22), followed by tilt-implanting second ions of the second conductivity over the trench at a second angle, thereby forming a second implanted region (24). The first angle is larger than the second angle, and the first implanted region and the second implanted region together form a bottom cell plate of the trench capacitor.

Abstract: A method for fabricating a Read Only Memory, (ROM), cell on a semiconductor substrate with device region and programmable cell region. The method includes the followed step. A plurality of field oxide regions is formed on the semiconductor substrate. A P-well and an N-well are formed in the device region of the semiconductor substrate, a P-well is formed in the programmable cell region of the substrate. A photoresist is formed over the N-well in the device region. Next, a phosphorus ion implantation is performed into the P-well in the device region for anti-punchthrough and into the N-well in the programmable region to form buried channel by using the photoresist layer as implant mask. After removing the photoresisit, a CMOS transistor is formed on the device region, and a NMOS transistor is formed on the programmable cell region.

Abstract: A MOS transistor with a self-aligned silicide and a lightly doped drain ballast resistor for ESD protection on a semiconductor substrate is formed with the method in the present invention. The ESD protection devices in a ESD protective region are formed at the same time with the forming of the NMOS, PMOS, or both in a functional region. The transistors with a lightly doped drain (LDD) structure and an ultra-shallow junction can be manufactured. The short channel effect and it's accompanying hot carrier effect is eliminated. ESD damage from external connections to the integrated circuits are kept from the densely packed devices. The self-aligned silicide (salicide) technology employed in the present invention for forming low resistance contacts provides high operation speed with low heat generation. Integrated circuits with ESD hardness and high circuit operation speed of the functional devices are provided by the semiconductor manufacturing process employing the method disclosed.

Abstract: The present invention is a method of manufacturing a high density capacitor for use in semiconductor memories. High etching selectivity between BPSG (borophosphosilicate glass) and CVD-oxide (chemical vapor deposition oxide) is used to fabricate a capacitor with a plurality of horizontal fins. First, a nitride layer is formed on a semiconductor substrate. A first conductive layer is then formed on the nitride layer. A stacked layer consists of BPSG and silicon oxide formed on the first conductive layer. Then a contact hole is formed in the stacked layer, the first conductive layer and the nitride layer. A highly selective etching is then used to etch the BPSG sublayers of the stacked layer. Next, a second polysilicon layer is formed in the contact hole and on the stacked layer, subsequently, a dielectric layer is formed on the second polysilicon layer. Then photolithography and etching processes are used to define the storage node.

Abstract: The method of the present invention is a method to fabricate a MOS device without boron penetration. After growing a gate oxide layer, a thin stacked-amorphous-silicon layer (SAS) is deposited over the oxide layer. Subsequently, a lightly nitrogen ion is implanted into the stacked-amorphous silicon layer. The stacked-amorphous silicon layer is patterned to define a gate structure. Then, a light doped ion implantation is performed to dope ions through the gate oxide layer into the substrate to form lightly doped source and drain regions. A dielectric layer is formed over the gate structure and the gate oxide layer, and the dielectric layer is etched to form sidewall spacers. Next, a second ion implantation is performed to dope ions into the substrate to form source and drain. Finally, a thermal annealing is performed on the stacked-amorphous silicon gate and the substrate.

Abstract: The present invention proposes a method for fabricating field oxide regions for isolation by an improved poly-buffered local oxidation of silicon (PBLOCOS) process. A polysilicon layer is utilized to reduce the bird's beak, and a thin thermal oxide film is formed on the buffered polysilicon film to prevent pitting formation. Forming a thin pad oxide and a silicon layer, a thermal oxidation is carried out to grow another pad oxide on the silicon layer and crystallize the silicon into polysilicon. The buffered layer of stacked oxide-polysilicon-oxide layer is thus formed. The silicon nitride layer is then deposited on the stacked buffered layer and the active areas are defined. A thermal oxidation is now performed, and thick field oxide regions are grown. After the masking nitride layer and the stacked buffered layer are stripped, the MOS devices are fabricated, and thus complete the present invention.