Patents by Inventor Simon Fenney

Simon Fenney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230326139
    Abstract: A method and apparatus for rendering a computer-generated image using a stencil buffer is described. The method divides an arbitrary closed polygonal contour into first and higher level primitives, where first level primitives correspond to contiguous vertices in the arbitrary closed polygonal contour and higher level primitives correspond to the end vertices of consecutive primitives of the immediately preceding primitive level. The method reduces the level of overdraw when rendering the arbitrary polygonal contour using a stencil buffer compared to other image space methods. A method of producing the primitives in an interleaved order, with second and higher level primitives being produced before the final first level primitives of the contour, is described which improves cache hit rate by reusing more vertices between primitives as they are produced.
    Type: Application
    Filed: June 2, 2023
    Publication date: October 12, 2023
    Inventor: Simon Fenney
  • Publication number: 20230274503
    Abstract: Hardware tessellation units include a sub-division logic block that comprises hardware logic arranged to perform a sub-division of a patch into two (or more) sub-patches. The hardware tessellation units also include a decision logic block that is configured to determine whether a patch is to be sub-divided or not and one or more hardware elements that control the order in which tessellation occurs. In various examples, this hardware element is a patch stack that operates a first-in-last-out scheme and in other examples, there are one or more selection logic blocks that are configured to receive patch data for more than one patch or sub-patch and output the patch data for a selected one of the received patches or sub-patches.
    Type: Application
    Filed: May 1, 2023
    Publication date: August 31, 2023
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Patent number: 11741659
    Abstract: Determining whether a ray intersects a 3D axis-aligned box identifies the front-facing plane of the box which intersects the ray at a position furthest along a direction of the ray. Whether the ray intersects the box is determined by whether the ray intersects the identified front-facing plane at a position that is no further along the ray than positions at which the ray intersects the back-facing planes in a subset of the dimensions. The subset of dimensions comprises the two dimensions for which the front-facing plane was not identified, but does not comprise the dimension for which the front-facing plane was identified. Whether the ray intersects the box is determined without performing a test to determine whether the ray intersects the identified front-facing plane at a position that is no further along the ray than a position at which the ray intersects the back-facing plane in the front-facing plane dimension.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: August 29, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Gregory Clark, Simon Fenney
  • Patent number: 11740470
    Abstract: A graphics processing system for a head mounted display (or other non-standard projection display) comprises a low latency distortion unit which is separate from a graphics processing unit in the graphics processing system. The low latency distortion unit receives pixel data generated by the graphics processing system using a standard projection and performs a mapping operation to introduce distortion which is dependent upon the optical properties of the optical arrangement within the head mounted display. The distorted pixel data which is generated by the low latency distortion unit is then output to the display in the head mounted display.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: August 29, 2023
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Patent number: 11741655
    Abstract: A method and an intersection testing module in a ray tracing system for determining whether a ray intersects a three-dimensional axis-aligned box. It is determined whether a first condition is satisfied, wherein the first condition is, or is equivalent to, ? "\[LeftBracketingBar]" C x - C z ? D x D z ? "\[RightBracketingBar]" ? H z ? D x D z + H x . It is determined whether a second condition is satisfied, wherein the second condition is, or is equivalent to, ? "\[LeftBracketingBar]" C y - C z ? D y D z ? "\[RightBracketingBar]" ? H z ? D y D z + H y . It is determined whether a third condition is satisfied, wherein the third condition is, or is equivalent to, ? "\[LeftBracketingBar]" C x ? D y D z - C y ? D x D z ? "\[RightBracketingBar]" ? H y ? D x D z + H x ? D y D z .
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: August 29, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Simon Fenney, Rostam King, Peter Smith-Lacey, Gregory Clark
  • Publication number: 20230262269
    Abstract: A method of compressing image data comprising a set of image values each representing a position in image-value space so as to define an occupied region thereof. The method comprises selectively applying a series of compression transforms to subsets of the image data items to generate a transformed set of image data items occupying a compacted region of value space. The method further comprises identifying a set of one or more reference data items that quantizes the compacted region in value space. For each image data item in the set of image data items, a sequence of decompression transforms from a fixed set of decompression transforms is identified that generates an approximation of that image data item when applied to a selected one of the one or more reference data items. Each image data item in the set of image data items is encoded as a representation of the identified sequence of decompression transforms for that image data item.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 17, 2023
    Inventor: Simon Fenney
  • Publication number: 20230252718
    Abstract: A hierarchical acceleration structure for use in a ray tracing system. When generating a node for the hierarchical acceleration structure, the primitives in a particular portion of the 3D scene may be alternatively bounded by different shaped volumes. These bounding volumes or ‘bounding regions’ can be Axis Aligned Bounding Boxes (AABBs), although other bounding volumes can be used. The ray tracing system may use sets of two or more bounding volumes in a 3D scene to bound all the primitives within that portion. The choice of how to create sets of multiple bounding volumes within a portion of the 3D scene may be done by using a binary space partition (BSP). Different sets of bounding regions may present different amounts of surface area for a hypothetical ray entering the portion of the 3D scene dependent upon the expected ray direction or angle.
    Type: Application
    Filed: November 30, 2022
    Publication date: August 10, 2023
    Inventors: Simon Fenney, Gregory Clark, Joseph John Davison
  • Patent number: 11715256
    Abstract: A method and an intersection testing module for performing intersection testing of a ray with a box in a ray tracing system. The ray and the box are defined in a 3D space using a space-coordinate system, and the ray is defined with a ray origin and a ray direction. A ray-coordinate system is used to perform intersection testing, wherein the ray-coordinate system has an origin at the ray origin, and the ray-coordinate system has three basis vectors. A first of the basis vectors is aligned with the ray direction. A second and a third of the basis vectors: (i) are both orthogonal to the first basis vector, (ii) are not parallel with each other, and (iii) have a zero as one component when expressed in the space-coordinate system. A result of performing the intersection testing is outputted for use by the ray tracing system.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: August 1, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Simon Fenney, Rostam King, Peter Smith-Lacey, Gregory Clark
  • Patent number: 11716094
    Abstract: Methods for converting an n-bit number into an m-bit number for situations where n>m and also for situations where n<m, where n and m are integers. The methods use truncation or bit replication followed by the calculation of an adjustment value which is applied to the replicated number.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: August 1, 2023
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Publication number: 20230232009
    Abstract: A method of converting 10-bit pixel data (e.g. 10:10:10:2 data) into 8-bit pixel data involves converting the 10-bit values to 7-bits or 8-bits and generating error values for each of the converted values. Two of the 8-bit output channels comprise a combination of a converted 7-bit value and one of the bits from the fourth input channel. A third 8-bit output channel comprises the converted 8-bit value and the fourth 8-bit output channel comprises the error values. In various examples, the bits of the error values may be interleaved when they are packed into the fourth output channel.
    Type: Application
    Filed: March 17, 2023
    Publication date: July 20, 2023
    Inventors: Ilaria Martinelli, Jeff Bond, Simon Fenney, Peter Malcolm Lacey, Gregory Clark
  • Patent number: 11682161
    Abstract: A method and an intersection testing module for performing intersection testing of a ray with a convex polygon in a ray tracing system. The ray and the convex polygon are defined in a 3D space using a space-coordinate system. The ray is defined with a ray origin and a ray direction. A ray-coordinate system is used to perform intersection testing, wherein the ray-coordinate system has an origin at the ray origin, and wherein the ray-coordinate system has three basis vectors. A first of the basis vectors is aligned with the ray direction. A second and a third of the basis vectors: (i) are both orthogonal to the first basis vector, (ii) are not parallel with each other, and (iii) have a zero as one component when expressed in the space-coordinate system. A result of performing the intersection testing is outputted for use by the ray tracing system.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: June 20, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Peter Smith-Lacey, Rostam King, Gregory Clark, Simon Fenney
  • Publication number: 20230186547
    Abstract: Intersection testing is performed for a ray with respect to a plurality of convex polygons, each of which is defined by an ordered set of vertices, wherein a shared vertex is used to define at least two of the convex polygons. The vertices of the convex polygons are projected onto a pair of axes orthogonal to the ray direction. A vertex ordering scheme defines an ordering of the projected vertices which is independent of the ordering of the vertices in the ordered sets. For each of the convex polygons, for each edge of the convex polygon defined by two of the projected vertices, a parameter indicative of which side of the edge the ray passes on is determined, wherein if the ray is determined to intersect a point on the edge then the parameter is determined based upon whether the ordering of the projected vertices defining the edge matches the ordering of the vertices in the ordered set of vertices defining the convex polygon.
    Type: Application
    Filed: February 8, 2023
    Publication date: June 15, 2023
    Inventors: Peter Smith-Lacey, Rostam King, Gregory Clark, Simon Fenney
  • Patent number: 11676335
    Abstract: A tessellation method uses vertex tessellation factors. For a quad patch, the method involves comparing the vertex tessellation factors for each vertex of the quad patch to a threshold value and if none exceed the threshold, the quad is sub-divided into two or four triangles. If at least one of the four vertex tessellation factors exceeds the threshold, a recursive or iterative method is used which considers each vertex of the quad patch and determines how to further tessellate the patch dependent upon the value of the vertex tessellation factor of the selected vertex or dependent upon values of the vertex tessellation factors of the selected vertex and a neighbor vertex. A similar method is described for a triangle patch.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: June 13, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Simon Fenney, Vasiliki Simaiaki
  • Patent number: 11677415
    Abstract: A method of data compression in which the total size of the compressed data is determined and based on that determination, the bit depth of the input data may be reduced before the data is compressed. The bit depth that is used may be determined by comparing the calculated total size to one or more pre-defined threshold values to generate a mapping parameter. The mapping parameter is then input to a remapping element that is arranged to perform the conversion of the input data and then output the converted data to a data compression element. The value of the mapping parameter may be encoded into the compressed data so that it can be extracted and used when subsequently decompressing the data.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: June 13, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Patent number: 11676337
    Abstract: Hardware tessellation units include a sub-division logic block that comprises hardware logic arranged to perform a sub-division of a patch into two (or more) sub-patches. The hardware tessellation units also include a decision logic block that is configured to determine whether a patch is to be sub-divided or not and one or more hardware elements that control the order in which tessellation occurs. In various examples, this hardware element is a patch stack that operates a first-in-last-out scheme and in other examples, there are one or more selection logic blocks that are configured to receive patch data for more than one patch or sub-patch and output the patch data for a selected one of the received patches or sub-patches.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: June 13, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Patent number: 11670048
    Abstract: A method and apparatus for rendering a computer-generated image using a stencil buffer is described. The method divides an arbitrary closed polygonal contour into first and higher level primitives, where first level primitives correspond to contiguous vertices in the arbitrary closed polygonal contour and higher level primitives correspond to the end vertices of consecutive primitives of the immediately preceding primitive level. The method reduces the level of overdraw when rendering the arbitrary polygonal contour using a stencil buffer compared to other image space methods. A method of producing the primitives in an interleaved order, with second and higher level primitives being produced before the final first level primitives of the contour, is described which improves cache hit rate by reusing more vertices between primitives as they are produced.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: June 6, 2023
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Patent number: 11657565
    Abstract: A method and system is provided for culling hidden objects in a tile-based graphics system before they are indicated in a display list for a tile. A rendering space is divided into a plurality of regions which may for example be a plurality of tiles or a plurality of areas into which one or more tiles are divided. Depth thresholds for the regions, which are used to identify hidden objects for culling, are updated when an object entirely covers a region and in dependence on a comparison between a depth value for the object and the depth threshold for the region. For example, if the depth threshold is a maximum depth threshold, the depth threshold may be updated if an object entirely covers the tile and the maximum depth value of the object is less than the maximum depth threshold.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: May 23, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, John W. Howson, Simon Fenney
  • Patent number: 11647234
    Abstract: A method of compressing image data comprising a set of image values each representing a position in image-value space so as to define an occupied region thereof. The method comprises selectively applying a series of compression transforms to subsets of the image data items to generate a transformed set of image data items occupying a compacted region of value space. The method further comprises identifying a set of one or more reference data items that quantizes the compacted region in value space. For each image data item in the set of image data items, a sequence of decompression transforms from a fixed set of decompression transforms is identified that generates an approximation of that image data item when applied to a selected one of the one or more reference data items. Each image data item in the set of image data items is encoded as a representation of the identified sequence of decompression transforms for that image data item.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: May 9, 2023
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Publication number: 20230089878
    Abstract: A lossy method of compressing data, such as image data, which uses wrap-around wavelet compression is described. Each data value is divided into two parts and the first parts, which comprise the most significant bits from the data values, are compressed using wrap-around wavelet compression. Depending upon the target compression ratio and the compression ratio achieved by compressing just the first parts, none, one or more bits from the second parts, or from a data value derived from the second parts, may be appended to the compressed first parts. The method described may be lossy or may be lossless. A corresponding decompression method is also described.
    Type: Application
    Filed: November 29, 2022
    Publication date: March 23, 2023
    Inventors: Linling Zhang, Simon Fenney
  • Patent number: 11611754
    Abstract: A method of converting 10-bit pixel data (e.g. 10:10:10:2 data) into 8-bit pixel data involves converting the 10-bit values to 7-bits or 8-bits and generating error values for each of the converted values. Two of the 8-bit output channels comprise a combination of a converted 7-bit value and one of the bits from the fourth input channel. A third 8-bit output channel comprises the converted 8-bit value and the fourth 8-bit output channel comprises the error values. In various examples, the bits of the error values may be interleaved when they are packed into the fourth output channel.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: March 21, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Ilaria Martinelli, Jeff Bond, Simon Fenney, Peter Malcolm Lacey, Gregory Clark