Patents by Inventor Simon Fenney

Simon Fenney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230082144
    Abstract: A graphics processing system includes a tiling unit configured to tile a scene into a plurality of tiles. A processing unit identifies tiles of the plurality of tiles that are each associated with at least a predetermined number of primitives. A memory management unit allocates a portion of memory to each of the identified tiles and does not allocate a portion of memory for each of the plurality of tiles that are not identified by the processing unit. A rendering unit renders each of the identified tiles and does not render tiles that are not identified by the processing unit.
    Type: Application
    Filed: November 18, 2022
    Publication date: March 16, 2023
    Inventors: Michael Worcester, Stuart Smith, Simon Fenney
  • Publication number: 20230066361
    Abstract: A tessellation method uses both vertex tessellation factors and displacement factors defined for each vertex of a patch, which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves calculating a vertex tessellation factor for each corner vertex in one or more input patches. Tessellation is then performed on the plurality of input patches using the vertex tessellation factors. The tessellation operation involves adding one or more new vertices and calculating a displacement factor for each newly added vertex. A world space parameter for each vertex is subsequently determined by calculating a target world space parameter for each vertex and then modifying the target world space parameter for a vertex using the displacement factor for that vertex.
    Type: Application
    Filed: October 19, 2022
    Publication date: March 2, 2023
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Patent number: 11593986
    Abstract: A method and an intersection testing module in a ray tracing system for performing intersection testing for a ray with respect to a plurality of convex polygons, each of which is defined by an ordered set of vertices, wherein at least one of the vertices is a shared vertex which is used to define at least two of the convex polygons. The vertices of the convex polygons are projected onto a pair of axes orthogonal to the ray direction. A vertex ordering scheme defines an ordering of the projected vertices which is independent of the ordering of the vertices in the ordered sets.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: February 28, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Peter Smith-Lacey, Rostam King, Gregory Clark, Simon Fenney
  • Patent number: 11587290
    Abstract: A graphics processing system includes a tiling unit configured to tile a first view of a scene into a plurality of tiles, a processing unit configured to identify a first subset of the tiles that are associated with regions of the scene that are viewable in a second view, and a rendering unit configured to render to a render target each of the identified tiles.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: February 21, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Simon Fenney, Michael Worcester, Stuart Smith
  • Publication number: 20230038325
    Abstract: A method of compressing data is described in which the compressed data is generated by either or both of a primary compression unit or a reserve compression unit in order that a target compression threshold is satisfied. If a compressed data block generated by the primary compression unit satisfies the compression threshold, that block is output. However, if the compressed data block generated by the primary compression unit is too large, such that the compression threshold is not satisfied, a compressed data block generated by the reserve compression unit using a lossy compression technique, is output.
    Type: Application
    Filed: October 20, 2022
    Publication date: February 9, 2023
    Inventor: Simon Fenney
  • Publication number: 20230031189
    Abstract: A ray tracing system and method for processing data in which a forward transformation indication is received defining a transformation from a first space to a second space. A transformation is performed on input data from the second space to the first space to determine transformed data by performing a reverse translation operation on the input data, wherein the reverse translation operation is the reverse of a translation defined by the forward transformation indication. An inverse linear mapping operation is performed on the result of the reverse translation operation, wherein the inverse linear mapping operation is the inverse of a linear mapping defined by the forward transformation indication. The transformed data is processed in the ray tracing system.
    Type: Application
    Filed: June 27, 2022
    Publication date: February 2, 2023
    Inventors: Rostam King, Gregory Clark, Simon Fenney
  • Patent number: 11532068
    Abstract: A graphics processing system has a tiling unit that tiles a first view of a scene into multiple tiles and generates a list of primitives associated with each tile. A processing unit identifies a first subset of the tiles that are each associated with at least a predetermined number of primitives in dependence on the list. A rendering unit then renders each of the identified tiles to a render target.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: December 20, 2022
    Assignee: Imagination Technologies Limited
    Inventors: Michael Worcester, Stuart Smith, Simon Fenney
  • Patent number: 11531479
    Abstract: A lossy method of compressing data, such as image data, which uses wrap-around wavelet compression is described. Each data value is divided into two parts and the first parts, which comprise the most significant bits from the data values, are compressed using wrap-around wavelet compression. Depending upon the target compression ratio and the compression ratio achieved by compressing just the first parts, none, one or more bits from the second parts, or from a data value derived from the second parts, may be appended to the compressed first parts. The method described may be lossy or may be lossless. A corresponding decompression method is also described.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: December 20, 2022
    Assignee: Imagination Technologies Limited
    Inventors: Linling Zhang, Simon Fenney
  • Publication number: 20220375153
    Abstract: A method and an intersection testing module in a ray tracing system for determining whether a ray intersects a three-dimensional axis-aligned box. It is determined whether a first condition is satisfied, wherein the first condition is, or is equivalent to, ? "\[LeftBracketingBar]" C x - C z ? D x D z ? "\[RightBracketingBar]" ? H z ? D x D z + H x . It is determined whether a second condition is satisfied, wherein the second condition is, or is equivalent to, ? "\[LeftBracketingBar]" C y - C z ? D y D z ? "\[RightBracketingBar]" ? H z ? D y D z + H y . It is determined whether a third condition is satisfied, wherein the third condition is, or is equivalent to, ? "\[LeftBracketingBar]" C x ? D y D z - C y ? D x D z ? "\[RightBracketingBar]" ? H y ? D x D z + H x ? D y D z .
    Type: Application
    Filed: March 23, 2022
    Publication date: November 24, 2022
    Inventors: Simon Fenney, Rostam King, Peter Smith-Lacey, Gregory Clark
  • Patent number: 11509330
    Abstract: A method of compressing data is described in which the compressed data is generated by either or both of a primary compression unit or a reserve compression unit in order that a target compression threshold is satisfied. If a compressed data block generated by the primary compression unit satisfies the compression threshold, that block is output. However, if the compressed data block generated by the primary compression unit is too large, such that the compression threshold is not satisfied, a compressed data block generated by the reserve compression unit using a lossy compression technique, is output.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: November 22, 2022
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Patent number: 11501494
    Abstract: A tessellation method uses both vertex tessellation factors and displacement factors defined for each vertex of a patch, which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves calculating a vertex tessellation factor for each corner vertex in one or more input patches. Tessellation is then performed on the plurality of input patches using the vertex tessellation factors. The tessellation operation involves adding one or more new vertices and calculating a displacement factor for each newly added vertex. A world space parameter for each vertex is subsequently determined by calculating a target world space parameter for each vertex and then modifying the target world space parameter for a vertex using the displacement factor for that vertex.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: November 15, 2022
    Assignee: Imagination Technologies Limited
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Publication number: 20220351459
    Abstract: A method and an intersection testing module in a ray tracing system for performing intersection testing for a ray with respect to a plurality of convex polygons, each of which is defined by an ordered set of vertices. The vertices of the convex polygons are projected onto a pair of axes orthogonal to the ray direction. For each edge of a convex polygon defined by two of the projected vertices, a signed parameter is determined, wherein the sign of the signed parameter is indicative of which side of the edge the ray passes on. If the ray is determined to intersect a point on the edge then the sign of the signed parameter is determined using a module which is configured to: take as inputs, indications which classify each of pi, qi, pj and qj coordinates as negative, zero or positive, and output, for valid combinations of classifications of the pi, qi, pj and qj coordinates, an indication of the sign of the signed parameter.
    Type: Application
    Filed: March 22, 2022
    Publication date: November 3, 2022
    Inventors: Peter Smith-Lacey, Rostam King, Gregory Clark, Simon Fenney
  • Publication number: 20220351458
    Abstract: A method and an intersection testing module for performing intersection testing of a ray with a convex polygon in a ray tracing system. The ray and the convex polygon are defined in a 3D space using a space-coordinate system. The ray is defined with a ray origin and a ray direction. A ray-coordinate system is used to perform intersection testing, wherein the ray-coordinate system has an origin at the ray origin, and wherein the ray-coordinate system has three basis vectors. A first of the basis vectors is aligned with the ray direction. A second and a third of the basis vectors: (i) are both orthogonal to the first basis vector, (ii) are not parallel with each other, and (iii) have a zero as one component when expressed in the space-coordinate system. A result of performing the intersection testing is outputted for use by the ray tracing system.
    Type: Application
    Filed: March 21, 2022
    Publication date: November 3, 2022
    Inventors: Peter Smith-Lacey, Rostam King, Gregory Clark, Simon Fenney
  • Publication number: 20220351460
    Abstract: A method and an intersection testing module for performing intersection testing of a ray with a box in a ray tracing system. The ray and the box are defined in a 3D space using a space-coordinate system, and the ray is defined with a ray origin and a ray direction. A ray-coordinate system is used to perform intersection testing, wherein the ray-coordinate system has an origin at the ray origin, and the ray-coordinate system has three basis vectors. A first of the basis vectors is aligned with the ray direction. A second and a third of the basis vectors: (i) are both orthogonal to the first basis vector, (ii) are not parallel with each other, and (iii) have a zero as one component when expressed in the space-coordinate system. A result of performing the intersection testing is outputted for use by the ray tracing system.
    Type: Application
    Filed: March 23, 2022
    Publication date: November 3, 2022
    Inventors: Simon Fenney, Rostam King, Peter Smith-Lacey, Gregory Clark
  • Publication number: 20220351457
    Abstract: A method and an intersection testing module in a ray tracing system for performing intersection testing for a ray with respect to a plurality of convex polygons, each of which is defined by an ordered set of vertices, wherein at least one of the vertices is a shared vertex which is used to define at least two of the convex polygons. The vertices of the convex polygons are projected onto a pair of axes orthogonal to the ray direction. A vertex ordering scheme defines an ordering of the projected vertices which is independent of the ordering of the vertices in the ordered sets.
    Type: Application
    Filed: March 21, 2022
    Publication date: November 3, 2022
    Inventors: Peter Smith-Lacey, Rostam King, Gregory Clark, Simon Fenney
  • Publication number: 20220335678
    Abstract: Methods and intersection testing modules are provided for determining, in a ray tracing system, whether a ray intersects a 3D axis-aligned box representing a volume defined by a front-facing plane and a back-facing plane for each dimension. The front-facing plane of the box which intersects the ray furthest along the ray is identified. It is determined whether the ray intersects the identified front-facing plane at a position that is no further along the ray than positions at which the ray intersects the back-facing planes in a subset of the dimensions, and this determination is used to determine whether the ray intersects the axis-aligned box. The subset of dimensions comprises the two dimensions for which the front-facing plane was not identified, but does not comprise the dimension for which the front-facing plane was identified.
    Type: Application
    Filed: March 22, 2022
    Publication date: October 20, 2022
    Inventors: Gregory Clark, Simon Fenney
  • Publication number: 20220327780
    Abstract: A tessellation method uses tessellation factors defined for each vertex of a patch which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves comparing the vertex tessellation factors to a threshold. If the vertex tessellation factors for either a left vertex or a right vertex, which define an edge of an initial patch, exceed the threshold, the edge is sub-divided by the addition of a new vertex which divides the edge into two parts and two new patches are formed. New vertex tessellation factors are calculated for each vertex in each of the newly formed patches, both of which include the newly added vertex. The method is then repeated for each of the newly formed patches until none of the vertex tessellation factors exceed the threshold.
    Type: Application
    Filed: June 20, 2022
    Publication date: October 13, 2022
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Publication number: 20220286142
    Abstract: Methods for converting an n-bit number into an m-bit number for situations where n>m and also for situations where n<m, where n and m are integers. The methods use truncation or bit replication followed by the calculation of an adjustment value which is applied to the replicated number.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 8, 2022
    Inventor: Simon Fenney
  • Publication number: 20220270320
    Abstract: Implementations of blender hardware perform both domain shading and blending and whilst some vertices may not require blending, all vertices require domain shading. The blender hardware includes a cache and/or a content addressable memory and these data structures are used to reduce duplicate domain shading operations.
    Type: Application
    Filed: May 13, 2022
    Publication date: August 25, 2022
    Inventors: Peter Malcolm Lacey, Simon Fenney, Tobias Hector, Ian King
  • Publication number: 20220270325
    Abstract: Hardware tessellation units include a sub-division logic block that comprises hardware logic arranged to perform a sub-division of a patch into two (or more) sub-patches. The hardware tessellation units also include a decision logic block that is configured to determine whether a patch is to be sub-divided or not and one or more hardware elements that control the order in which tessellation occurs. In various examples, this hardware element is a patch stack that operates a first-in-last-out scheme and in other examples, there are one or more selection logic blocks that are configured to receive patch data for more than one patch or sub-patch and output the patch data for a selected one of the received patches or sub-patches.
    Type: Application
    Filed: April 29, 2022
    Publication date: August 25, 2022
    Inventors: Peter Malcolm Lacey, Simon Fenney