Abstract: A stacked semiconductor memory device includes memory device contacts to externally connect the stacked semiconductor memory device to a printed circuit board. In a dual or quad stack configuration, the stacked semiconductor memory device includes a first package which is stacked above a second package. The first and second packages are preferably designed as FBGA packages, each of them including package contacts. By providing first and second flexible circuit structures to connect the package contacts of the first and second packages to the memory device contacts, a symmetrical stacked package configuration is obtained. This configuration facilitates transmission of signals with improved signal integrity via a bus of the printed circuit board between the stacked semiconductor memory device and a controller chip, even if the frequency of the bus or the load of the stacked semiconductor memory is increased.

Abstract: A circuit system includes a means for controlling a first and a second memory unit by means of a differential control signal. The differential control signal includes a first control signal and a second control signal, which is inverted to the first control signal. Further, the circuit system comprises a differential control signal line, which includes a first signal line for routing the first control signal and a second signal line for routing the second control signal. The first switching unit is connected via the first signal line and the second circuit unit is connected via the second signal line to the means for controlling.

Abstract: The present invention relates to a semiconductor device which provides a shortest possible connection between two semiconductor components 10a and 10b arranged in a manner lying opposite on a substrate 2. The two semiconductor components 10a and 10b are in each case arranged with their chip contact-connection regions 11a and 11b facing the substrate 2. A vertical through-plating device 20 connects the two chip contact-connection regions 11a and 11b.

Abstract: A method and a device adapt/tune signal transit times on line systems or networks between integrated circuits which are mounted on printed circuit boards. Fine tuning of differences in transit times can be easily carried out by capacitive load structures disposed on conductor tracks in the vicinity of chip housings of the integrated circuits on the printed circuit boards by disconnecting connecting lines using a cutting laser.

Abstract: Interface parameters for a plurality of semiconductor devices, particularly parameters for output drivers (i.e. on chip driver) and terminations (i.e. on die termination) for double data rate dynamic random access memories, are aligned using a calibration reference which is common to the semiconductor devices and is connected to calibration connections on the semiconductor devices. The semiconductor devices are calibrated in succession, in each case individually, and the calibration connection on the respective semiconductor device which is currently performing calibration is connected to an internal calibration unit by an internal switching unit in the process, and the calibration connections on all other semiconductor devices are terminated to a high impedance internally.

Abstract: An integrated circuit which is integrated in a housing having connecting pins fitted to the housing for connecting the housing to signal lines of an external circuit, each connecting pin connected by an associated wiring line to a contact pad of the circuit integrated in the housing, to exchange signals between the external circuit and the integrated circuit, where to minimize the line lengths of the associated wiring lines, the connecting pins to be connected to signal lines for high-frequency signals are fitted centrally to the housing.

Abstract: A method and a device for time measurement at a designated signal pin or associated solder pad on a semiconductor module on which semiconductor chips are mounted using the ball-grid-array technique. Integrated on the semiconductor module in the direct vicinity of a solder pad associated with the signal pin to be measured is an equivalent conductor pattern, which can be loaded with passive components in such a way that, in the loaded state, it forms an equivalent load circuit for the designated signal pin which simulates the time-relevant characteristic electrical values of the designated signal pin. The measurement takes place after connection of the ELC to a solder pad associated with the signal pin, with the semiconductor chip detached from the semiconductor module.

Abstract: A semiconductor component package configuration includes a semiconductor chip mounted to a printed circuit board, and a substrate arranged between the semiconductor chip and the printed circuit board. The substrate is for routing the wiring terminals of the semiconductor chip to the printed circuit board. The substrate is connected to the printed circuit board by solder joints. A filler between the semiconductor chip and the substrate mechanically isolates the semiconductor chip and the solder joints. A metal layer, which is connected to solder joints, is applied to the substrate. At least one molded element of heat-dissipating material is applied to the metal layer and is connected in a heat-conducting manner to the metal layer. This provides the package configuration with an improved capability of conducting the lost power that is dissipated from the installed semiconductor chip, and the desired mechanical properties of the package arrangement are retained.

Abstract: A method and a device for time measurement at a designated signal pin or associated solder pad on a semiconductor module on which semiconductor chips are mounted using the ball-grid-array technique. Integrated on the semiconductor module in the direct vicinity of a solder pad associated with the signal pin to be measured is an equivalent conductor pattern, which can be loaded with passive components in such a way that, in the loaded state, it forms an equivalent load circuit for the designated signal pin which simulates the time-relevant characteristic electrical values of the designated signal pin. The measurement takes place after connection of the ELC to a solder pad associated with the signal pin, with the semiconductor chip detached from the semiconductor module.

Abstract: A circuit module has a circuit board, multiple circuit units on the circuit board and at least one clock input on the circuit board for receiving an external clock signal. The circuit module has a first PLL unit on the circuit board for providing an internal clock signal based on the external clock signal to at least a first one of the circuit units. In addition, the circuit module has a second PLL unit on the circuit board for providing an internal clock signal based on the external clock signal to at least a second one of the circuit units.

Abstract: A lead frame is described which has at least one integrated electronic circuit. The integrated electronic circuit is situated in a region of a main area of the lead frame. The lead frame has at least one signal line, at least one electrically insulating plate, and an electrically conductive, grounded plate are situated. The electrically insulating plate, and the electrically conductive, grounded plate are situated, at least in sections, between the integrated electronic circuit and the signal line. A method for producing the lead frame is also described.

Abstract: The present invention provides an apparatus for connecting semiconductor modules, in particular memory banks, having: at least two devices (A, B) for receiving a respective semiconductor module (1, 2); a contact device (13a, 13b, 13c, 13d, 13e, 13f) having a first group of contacts (13a, 13b, 13c, 13d) and a second group of contacts (13e, 13f), the two groups being able to be connected to one another by means of a variable connection module (3, 4); a group of lines (10, 11, 20, 21) for connecting the receiving devices (A, B) to the first group of contacts (13a, 13b, 13c, 13d), a subgroup (13b, 13c) of the first group of contacts being assigned to the lines (10, 11) of the first receiving device (A); the connection module (3, 4) connecting either a subgroup of the contacts (13b, 13c) to the second group of contacts (13e, 13f), or the first group of contacts (13a, 13b, 13c, 13d) to the second group of contacts (13e, 13f).

Abstract: The invention relates to a semiconductor component, in particular memory module, having a carrier board and semiconductor chips, in particular memory chips, the semiconductor chips being fitted on the carrier board such that the main planes thereof run perpendicular to the carrier boards. Furthermore, the invention relates to a method for producing semiconductor components.

Abstract: Integrated circuit which is integrated in a housing and has a plurality of connecting pins fitted to the housing for connecting the housing to signal lines of an external circuit,

Abstract: A semiconductor module having a configurable data width of an output bus has data connecting pads as well as driver circuits having a respective output that is connected to an associated data connecting pad. At least one of the data connecting pads, which is not used for interchanging data or commands during operation, is permanently connected to a connection for an internal supply voltage. Thus, in a module configuration with a reduced number of data lines being used, the remaining data lines can be operated at an increased frequency, since the signal-to-ground ratio is improved.

Abstract: Interface parameters for a plurality of semiconductor devices, particularly parameters for output drivers (i.e. on chip driver) and terminations (i.e. on die termination) for double data rate dynamic random access memories, are aligned using a calibration reference which is common to the semiconductor devices and is connected to calibration connections on the semiconductor devices. The semiconductor devices are calibrated in succession, in each case individually, and the calibration connection on the respective semiconductor device which is currently performing calibration is connected to an internal calibration unit by an internal switching unit in the process, and the calibration connections on all other semiconductor devices are terminated to a high impedance internally.

Abstract: The present invention relates to an apparatus and a method for reducing reflexions in a bus for transmitting data. The device comprises an output, which is connected to an input of the bus, a device for sending a test signal into the input of the bus (102), the device for sending being connected to the output, a device for receiving reflexions from the bus, which is connected to the output, and a device for evaluating the reflexions from the bus, in order to supply an evaluation result, and for setting an impedance at the output as a function of the evaluation result, in order to reduce the reflexions from the bus.

Abstract: The present invention provides an apparatus for connecting semiconductor modules, in particular memory banks, having: at least two devices (A, B) for receiving a respective semiconductor module (1, 2); a contact device (13a, 13b, 13c, 13d, 13e, 13f) having a first group of contacts (13a, 13b, 13c, 13d) and a second group of contacts (13e, 13f), the two groups being able to be connected to one another by means of a variable connection module (3, 4); a group of lines (10, 11, 20, 21) for connecting the receiving devices (A, B) to the first group of contacts (13a, 13b, 13c, 13d), a subgroup (13b, 13c) of the first group of contacts being assigned to the lines (10, 11) of the first receiving device (A); the connection module (3, 4) connecting either a subgroup of the contacts (13b, 13c) to the second group of contacts (13e, 13f), or the first group of contacts (13a, 13b, 13c, 13d) to the second group of contacts (13e, 13f).

Abstract: A semiconductor module having a configurable data width of an output bus has data connecting pads as well as driver circuits having a respective output that is connected to an associated data connecting pad. At least one of the data connecting pads, which is not used for interchanging data or commands during operation, is permanently connected to a connection for an internal supply voltage. Thus, in a module configuration with a reduced number of data lines being used, the remaining data lines can be operated at an increased frequency, since the signal-to-ground ratio is improved.

Abstract: In order to mount a semiconductor chip on a carrier layer, consolidated filler material is applied between the semiconductor chip and the carrier layer. The filler material is sucked, under the application of a partial vacuum, from at least one edge section of the semiconductor chip to at least one other edge section of the semiconductor chip. As a result, a package is provided in which the filler material is essentially free of air inclusions.