Abstract: The present invention provides a circuit board for at least one memory component which has a housing and electrical contacts on the underside of the housing, the circuit board having a first surface and a second surface, contacts on the first surface of the circuit board which are assigned to the contacts of the at least one memory component, contact balls which connect the contacts of the at least one memory component to the assigned contacts of the circuit board, and conductor tracks having a first end and a second end, which are assigned to the contacts on the first surface of the circuit board and are connected at the first end to said contacts, the conductor tracks extending between their first end and their second end on a surface of the circuit board beyond the periphery of the housing of the at least one memory component.

Abstract: The invention relates to the arrangement of a plurality of memory chip housings, each having at least one memory chip arranged in the interior of the memory chip housing and having a plurality of pins, which are led out of the respective memory chip housing, on a DIMM circuit board which, on one long side, has a multipole contact rail for insertion into a base of a mother board, where the plurality of memory chip housings (2) [lacuna] arranged in two rows (6, 7) parallel to the long side (3) of the circuit board (1).

Abstract: The present invention relates to an apparatus and a method for reducing reflexions in a bus for transmitting data. The device comprises an output, which is connected to an input of the bus, a device for sending a test signal into the input of the bus (102), the device for sending being connected to the output, a device for receiving reflexions from the bus, which is connected to the output, and a device for evaluating the reflexions from the bus, in order to supply an evaluation result, and for setting an impedance at the output as a function of the evaluation result, in order to reduce the reflexions from the bus.

Abstract: The memory system has data lines for transmitting data between memory components and at least one control unit. The memory system is a distributed system with at least one central control unit and at least one group control unit, the group control unit having at least one first data line for connecting the group control unit to the central control unit, and second data lines for connecting a group of memory components to the group control unit.

Abstract: An IC chip is described that has a number of connecting devices, to which a specific predetermined pin assignment is respectively assigned and the pin assignment is provided more than once. The IC chip can be mounted optionally in a standard wiring, resulting from the pin assignment, or in a mirror-image wiring, mirror-inverted in relation to the standard wiring, likewise resulting from the pin assignment. To be able to produce such a chip at low cost and mount it in a simple manner, it is proposed that at least two groups of metallic bonding pads, which are disposed on the upper side or underside of the IC chip, are provided as the connecting devices and that the first group of bonding pads are assigned the standard wiring or standard pin assignment and at least a second group of bonding pads is assigned the corresponding mirror-image wiring or mirror-image pin assignment.

Abstract: The memory system has data lines for transmitting data between memory components and at least one control unit. The memory system is a distributed system with at least one central control unit and at least one group control unit, the group control unit having at least one first data line for connecting the group control unit to the central control unit, and second data lines for connecting a group of memory components to the group control unit.

Abstract: The invention relates to a method and to a device for adapting/tuning signal transit times on line systems or networks between integrated circuits which are mounted on printed circuit boards. Fine tuning of differences in transit times can be easily carried out by capacitive load structures disposed on conductor tracks (3-9) in the vicinity of chip housings of the integrated circuits on the printed circuit boards by disconnecting connecting lines (20, 21) using a cutting laser.

Abstract: A lead frame is described which has at least one integrated electronic circuit. The integrated electronic circuit is situated in a region of a main area of the lead frame. The lead frame has at least one signal line, at least one electrically insulating plate, and an electrically conductive, grounded plate are situated. The electrically insulating plate, and the electrically conductive, grounded plate are situated, at least in sections, between the integrated electronic circuit and the signal line. A method for producing the lead frame is also described.

Abstract: A VSMP semiconductor component is mounted by inserting an auxiliary element into a slot in a receptacle. The auxiliary element projects laterally from a narrow side of the semiconductor component and, as the auxiliary element is inserted into the slot, the semiconductor component is properly positioning on the printed circuit board.