Abstract: A method for identifying a cell quality during cell formation includes: conducting a beginning of life cycling following an initial cell formation charge of multiple cells; collecting and preprocessing a discharge data set generated by one of the multiple cells during the beginning of life cycling; calculating a statistical variance from the discharge data set identifying an estimated probability of meeting a target cell usage time; and projecting a life span of the multiple cells.

Abstract: A system for an electric vehicle includes a hysteresis module configured to calculate a plurality of hysteresis state components of a battery based on a measured current and a respective hysteresis transit rate, calculate an overall hysteresis state of the battery based on the plurality of hysteresis state components, and calculate a hysteresis voltage of the battery based on the overall hysteresis state, and a state of charge (SOC) module configured to calculate an SOC of the battery based in part on the hysteresis voltage.

Abstract: A method of analyzing the quality of a battery cell includes performing a high-throughput quality check on the battery cell with a quality control system, assessing a quality score to the battery cell, with quality score identifying the battery cell as low-quality or high-quality, and performing a comprehensive quality check on the battery cell if identified as low-quality. The method further includes assessing an enhanced quality score to the battery cell superseding the quality score of the quality control system identifying the battery cell as confirmed low-quality or confirmed high-quality and providing revised production instructions for manufacturing successive battery cells if confirmed low-quality.

Abstract: A method for identifying a cell quality during cell formation includes: conducting a beginning of life cycling following an initial cell formation charge of multiple cells; collecting and preprocessing a discharge data set generated by one of the multiple cells during the beginning of life cycling; calculating a statistical variance from the discharge data set identifying an estimated probability of meeting a target cell usage time; and projecting a life span of the multiple cells.

Abstract: A method of analyzing the quality of a battery cell includes performing a high-throughput quality check on the battery cell with a quality control system, assessing a quality score to the battery cell, with quality score identifying the battery cell as low-quality or high-quality, and performing a comprehensive quality check on the battery cell if identified as low-quality. The method further includes assessing an enhanced quality score to the battery cell superseding the quality score of the quality control system identifying the battery cell as confirmed low-quality or confirmed high-quality and providing revised production instructions for manufacturing successive battery cells if confirmed low-quality.

Abstract: A method for hiding implicit bit corrections in a partial product adder array in a binary and hexadecimal floating-point multiplier such that no additional adder stages are needed for the implicit bit corrections. Two leading-one correction terms are generated for the fraction in the multiplier floating-point number and two leading-one correction terms are generated for the fraction in the multiplicand floating-point number. The floating-point numbers may be single-precision or double-precision. Each leading-one correction term for the single-precision case is appended to the left of an intermediate partial product sum in the adder array that is an input to an adder so as to not to extend the bits in the input further to the left than the bits in another input to the adder. Each leading-one correction term for the double-precision case replaces an adder input that is unused when base-2 floating-point numbers are multiplied.

Abstract: A method for hiding implicit bit corrections in a partial product adder array in a binary and hexadecimal floating-point multiplier such that no additional adder stages are needed for the implicit bit corrections. Two leading-one correction terms are generated for the fraction in the multiplier floating-point number and two leading-one correction terms are generated for the fraction in the multiplicand floating-point number. The floating-point numbers may be single-precision or double-precision. Each leading-one correction term for the single-precision case is appended to the left of an intermediate partial product sum in the adder array that is an input to an adder so as to not to extend the bits in the input further to the left than the bits in another input to the adder. Each leading-one correction term for the double-precision case replaces an adder input that is unused when base-2 floating-point numbers are multiplied.

Abstract: A method for operating a fused-multiply-add pipeline in a floating-point unit of a processor is disclosed. A multiplication is initially performed between a first operand and a second operand in a multiplier block to obtain a set of partial product results. The partial product results are sent to a carry-save adder block. A partial product reduction is performed on the partial product results to generate a carry-save result having a sum term and a carry term. The carry-save result is then formatted to generate a carry-out bit. The carry-save result is added to a third operand to generate a final result.

Abstract: A method for hiding implicit bit corrections in a partial product adder array in a binary and hexadecimal floating-point multiplier such that no additional adder stages are needed for the implicit bit corrections. Two leading-one correction terms are generated for the fraction in the multiplier floating-point number and two leading-one correction terms are generated for the fraction in the multiplicand floating-point number. The floating-point numbers may be single-precision or double-precision. Each leading-one correction term for the single-precision case is appended to the left of an intermediate partial product sum in the adder array that is an input to an adder so as to not to extend the bits in the input further to the left than the bits in another input to the adder. Each leading-one correction term for the double-precision case replaces an adder input that is unused when base-2 floating-point numbers are multiplied.

Abstract: A method for hiding implicit bit corrections in a partial product adder array in a binary and hexadecimal floating-point multiplier such that no additional adder stages are needed for the implicit bit corrections. Two leading-one correction terms are generated for the fraction in the multiplier floating-point number and two leading-one correction terms are generated for the fraction in the multiplicand floating-point number. The floating-point numbers may be single-precision or double-precision. Each leading-one correction term for the single-precision case is appended to the left of an intermediate partial product sum in the adder array that is an input to an adder so as to not to extend the bits in the input further to the left than the bits in another input to the adder. Each leading-one correction term for the double-precision case replaces an adder input that is unused when base-2 floating-point numbers are multiplied.

Abstract: A method for operating a fused-multiply-add pipeline in a floating-point unit of a processor is disclosed. A multiplication is initially performed between a first operand and a second operand in a multiplier block to obtain a set of partial product results. The partial product results are sent to a carry-save adder block. A partial product reduction is performed on the partial product results to generate a carry-save result having a sum term and a carry term. The carry-save result is then formatted to generate a carry-out bit. The carry-save result is added to a third operand to generate a final result.

Abstract: A system for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal but is much greater than the product of operands A and C, i.e. AC. By limiting the additional shift of B during normalization, by the number of leading zeros in opB, no increase is needed in the output bus of the alignment shifter. Furthermore, the additional shift may be done either in the alignment shifter, or postponed to a later stage in the pipeline, where the result is normalized.

Abstract: A floating point processor unit includes a shift amount calculation circuit within a normalizer portion of the floating point unit, wherein the shift amount calculation circuit is utilized to compute the normalizer shift amount for a log estimate instruction that runs as a pipelinable instruction.

Abstract: The present invention provides a scalable and reliable collaborative multicast routing for multicasting in hybrid, multi-tiered, mobile heterogeneous wireless networks. It establishes a multicast tree, maintains the established route, detects and prevents most link breakage within the multicast tree by a neighboring node or the cooperation of the neighboring node, and enables merging of partitioned multicast trees of the same multicast group by nodes that participate in one of the partitioned multicast trees. The use of local nodes to collaboratively establish, maintain, recover, and merge the hybrid, multi-tiered mobile wireless networks that use heterogeneous set of mobile wireless nodes is the fundamental basis for the collaborative multicast routing scheme of the present invention.

Abstract: A method, apparatus, and computer program product are presented for providing a measure of fault tolerance and security in the operation of cross layer communication agents (CCA) in a hybrid network. Specifically, this method, apparatus and computer program provide the detection and control necessary to prevent network disruptions due to failures, attacks, or link unavailability.

Abstract: A streaming data filtering method and apparatus utilizing users' profiles to deliver streaming data to users is presented. The invention uses context-based cues to extract content from both video and text ontologies. The invention provides novel techniques that semi-automatically generate a media concept hierarchy using hierarchical classifiers for representing text, closed-caption, and video features. This hierarchy is used to classify arrival of real-time news and will also be used to match users' profiles. Moreover, this hierarchy can be dynamically re-organized based upon user changes and arrival of real-time news. Matching a request with respect to a concept hierarchy is more efficient and reliable than searching specific keywords since the views of collected documents are refined as the hierarchy is traversed.

Abstract: A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes a mechanism for performing a shift or masking operation in response to determining that the operand is in an un-normalized format. The system also includes instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.

Abstract: A method and system for performing a binary mode and hexadecimal mode Multiply-Add floating point operation in a floating point arithmetic unit according to a formula A*C+B, wherein A, B and C operands each have a fraction and an exponent part expA, expB and expC and the exponent of the product A*C is calculated and compared to the exponent of the addend under inclusion of an exponent bias value dedicated to use unsigned biased exponents, wherein the comparison yields a shift amount used for aligning the addend with the product operand, wherein a shift amount calculation provides a common value CV for both binary and hexadecimal according to the formula (expA+expC?expB+CV).

Abstract: A floating point processor unit includes a shift amount calculation circuit within a normalizer portion of the floating point unit, wherein the shift amount calculation circuit is utilized to compute the normalizer shift amount for a log estimate instruction that runs as a pipelinable instruction.

Abstract: The present invention provides a scalable and reliable collaborative multicast routing for multicasting in hybrid, multi-tiered, mobile heterogeneous wireless networks. It establishes a multicast tree, maintains the established route, detects and prevents most link breakage within the multicast tree by a neighboring node or the cooperation of the neighboring node, and enables merging of partitioned multicast trees of the same multicast group by nodes that participate in one of the partitioned multicast trees. The use of local nodes to collaboratively establish, maintain, recover, and merge the hybrid, multi-tiered mobile wireless networks that use heterogeneous set of mobile wireless nodes is the fundamental basis for the collaborative multicast routing scheme of the present invention.