Abstract: A real-time multicast scheduler method and apparatus is presented, to facilitate multicasting of real-time variable bit rate data in wireless ad-hoc networks. Variable bit rate traffic cannot tolerate delay jitter. However, a small amount of packet losses may be tolerable. In order to ensure the provisioning of a desired level of quality of service, bandwidth is reserved on the multicast structure. A goal of the real-time multicast scheduler is to avoid packet collisions and to facilitate color re-use, where “color” is defined as a channel selected as a combination of time-division multiple access, frequency-division multiple access, and code-division multiple access schemes. The real-time multicast scheduler provides a self-healing network which corrects for disconnections caused by node movement and nodes moving out of range of each other, while accounting for colors already assigned for data transmission in order to prevent packet collisions.

Abstract: A predictive routing scheme for broad band Low Earth Orbit (LEO) satellite constellations is presented. The predictive routing scheme may be used to provide Quality of Service (QoS) guarantees for both Constant Bit-Rate (CBR) and Variable Bit-Rate (VBR) traffic types. The predictive routing scheme takes advantage of the predictable qualities of a LEO constellation, such as constant satellite footprint, constant satellite velocity, and predictable satellite trajectory. By using this information, combined with satellite-fixed cells which are divided into a set of equal-sized slots, along with user information such as the location of each particular user as well as the geographic concentrations of user traffic, each satellite may cooperate with surrounding satellites which have recently passed through the area into which they are entering, in order to receive predictive information regarding their future load.

Abstract: The present invention relates to improvements of out-of-order CPU architectures regarding performance purposes, and in particular to improved methods for serializing and committing instructions. It is proposed to split the prior art commit into at least two cooperating processes: a pre-committer and a ‘main’ committer. According to the invention the main committer is blocked until detecting (335) that a next sequential external instruction is ready for commitment.

Abstract: An Information Source 600 provides information to a Data Service element 602. A Directory Service Update Decision element 604 registers 606 with a Directory Service element 608. The client 610 provides a request to a Personal Lookup Agent element 612. The Directory Service Poll Decisions 614 queries the Directory Service element 608 with a Lookup 616 request. The Personal Lookup Agent 612 implements an interface to the Directory Service element 608 that allows the client 610 to ingest application-specific objects that encapsulates control functions for Directory Service Polling Decisions 614 for Candidate Service Filtering 618, and subsequent Target Service Filtering 620.

Abstract: A data flow system, where a source 100 transmits a reservation packet to an ingress element 102. The ingress element 102 polices incoming message traffic and collects data flow information. Quality of service differentiation is realized by marking data packets of different data flows. The ingress element 102 registers the reservation packet and forwards the request to a core router 106. The core router 106 evaluates the service level required, and available resources. Based on this evaluation the core router 106 will reject, accept, or modify the received message, indicate the price for the requested level of service, and forward the reservation packet. The process is repeated until the reservation packet reaches the destination 110, which sends a feedback message to the source 100 indicating the result of the reservation packet. After establishing a reservation, source 100 transmits periodic control messages and collects information regarding resource availability, and the flow path.

Abstract: The integration of multiple application programs on one chip card is described, whereby the application programs stored on it do not have access to each other, which is achieved through a separation and de-coupling of the individual programs from one another. A first embodiment has several mutually-independent units, consisting respectively of a processor unit and a memory unit. Communication of these independent units with the external world and also with each other takes place through a control unit. A communication of the independent units with each other can only take place through the respective processor units, so that the linked memory units may not be accessed by circumvention of the processor unit. In a further embodiment, the separation of different applications on a chip card with only one processor takes place through the insertion of a separation of the application segments in the memory area of the chip card.

Abstract: A method and apparatus for the determination of leading zero digits of a sum is presented herein. The technique incorporates the parallel determination of partial sums of single digits accounting for the possibility of carries and on the basis thereof the pre-determination of potential zero digits or potential leading zero digits. Upon the establishment of a correct partial sum, the potential zero digits are selected and evaluated thereby determining the leading zero digits. The invention may be implemented in an adder in parallel or via a hierarchical structure. The parallelism permits time-savings in the determination of a normalized sum. The invention is preferably incorporated into adders, floating point computing units and/or data processing units.

Abstract: A correction of microprocessor chip design errors is achieved by identifying selected sets of instructions and/or selected sets of instruction sequences in an erroneous control flow of the microprocessor and/or by identifying selected sets of interface control and status signals. A match selectively initiates a corrective action by interfering with the instruction flow in the microprocessor chip or by requesting external control from an associated processor unit. Alternatively, a match is used for a programmable modification of interface control and status signals to adapt the chip to changes of its environment without redesign.

Abstract: A pipeline floating point processor in which the addition pipelining is reorganized so that no wait cycle is needed when the addition uses the result of an immediately foregoing multiplication (fast multiply-add instruction). The reorganization implies the following changes of an existing data flow of the pipeline floating processor: data feed-back via path ND of normalized data from the multiplier M into the aligners AL1 and AL2; shift left one digit feature on both sides of the data path for taking account of a possible leading zero digit of the product, and special zeroing of potential guard digits by Z1 and Z2; exponent build by 9 bits for overflow and underflow recognition, and due to an underflow the exponent result, is reset to zero on the fly by a true zero unit (T/C).

Abstract: A self-checking complementary adder unit used for high performance subtractions comprises two carry select adders (30 and 36) each of which consists of a pair of byte or digit organized ripple carry adders (31, 32 and 37, 38) generating in parallel virtual sums from true and complemented operands based on the assumption that the carry-in signal is 1 or 0. Depending on byte or digit carry signals generated by carry look ahead circuits (33, 39), partial sums are selected from the virtual sums to form a real sum. The outputs of both carry select adders are connected to a multiplexer (42) which is controlled by the high order carry-out signal from one of the carry look ahead circuits representing the sign of a real sum. The multiplexer selects one of the real sums as the result of a subtraction. A sum checker compares cross-wise the parity bits of the virtual sums from both carry select adders and also compares the related carry-out signals from both the ripple carry adders and carry look ahead circuits.

Abstract: A digital circuit computes the logarithm of a number. The circuit makes the computation by first determining a multiplicity of factors f.sub.i from a predetermined set of factors such that the product of the multiplicity of factors f.sub.i and the number equals the base of the logarithm. A memory stores the logarithms of all the numbers in the predetermined set. The circuit then looks-up and sums the logarithms of the multiplicity of factors f.sub.i, and then subtracts the sum from one to yield the logarithm of the number.

Abstract: A multiplier for multiplying two binary operands is presented which comprises an encoding unit, a multiplying unit composed of two multiplying arrays, and a logic unit. The encoding unit to which the second operand is applied generates factors following the Booth algorithm. The two multiplying arrays are respectively applied with the first operand as well as with factors belonging to the higher significance digits or the lower significance digits, respectively, of the second operand. In both multiplying arrays the multiplication of the factors with the first operand into a respective partial end product is simultaneously performed. Both partial end products are applied to the logic unit which generates therefrom the end product in accordance with the algorithm used at the beginning.