Patents by Inventor Son Van Nguyen

Son Van Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7226876
    Abstract: Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: June 5, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Francimar Campana Schmitt, Li-Qun Xia, Son Van Nguyen, Shankar Venkataraman
  • Patent number: 7117583
    Abstract: A method and apparatus using a pre-patterned seed layer for providing an aligned coil for an inductive head structure. The method uses an aligned process where the base plate imprint is fabricated on an electrically insulating layer and the reversed image is fabricated and etched into the coil insulation material, e.g., hard bake photoresist to alleviate the problems associated with complete ion removal of the seed layer between high aspect ratio coils. The method would also not be prone to plating non-uniformities (voids), and would not be subject to seed layer undercutting in a wet etch step process.
    Type: Grant
    Filed: March 18, 2002
    Date of Patent: October 10, 2006
    Assignee: International Business Machines Corporation
    Inventors: Thomas Edward Dinan, Jeffrey S. Lille, Son Van Nguyen, Hugo Alberto Emilio Santini
  • Patent number: 7115534
    Abstract: Methods are provided for depositing a dielectric material for use as an anti-reflective coating and sacrificial dielectric material in damascene formation. In one aspect, a process is provided for processing a substrate including depositing an acidic dielectric layer on the substrate by reacting an oxygen-containing organosilicon compound and an acidic compound, depositing a photoresist material on the acidic dielectric layer, and patterning the photoresist layer. The acidic dielectric layer may be used as a sacrificial layer in forming a feature definition by etching a partial feature definition, depositing the acidic dielectric material, etching the remainder of the feature definition, and then removing the acidic dielectric material to form a feature definition.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: October 3, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Son Van Nguyen, Michael D. Armacost, Mehul Naik, Girish A. Dixit, Ellie Y. Yieh
  • Patent number: 7079355
    Abstract: A method for producing a magnetic transducer with an inductive write head having a multilayer coil with a high aspect ratio and a short yoke is disclosed. A damascene process is used for two coil layers and a conventional process for the third coil layer. The process of the invention allows a seed layer for the coil to be deposited on the side walls of the trenches for the first and second coil layers. In one embodiment the seed layer for the coil is preceded by an adhesion layer.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: July 18, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Richard D. Hsiao, Quang Le, Edward Hin Pong Lee, Paul Phong Nguyen, Son Van Nguyen, Denny D. Tang, Bradley Douglas Webb, Patrick Rush Webb, Samuel Wei-san Yuan
  • Patent number: 7075750
    Abstract: An apparatus for patterning a self-aligned coil using a damascene process is disclosed. Coil pockets are formed in a first insulation layer disposed over a first pole layer. A barrier/seed layer is deposited along walls of the coil pockets in the insulation layer. Copper is formed in the coil pockets and over the insulation layer. The copper is planarized down to the insulation layer. The self-aligned coil process packs more copper into the same coil pocket and relaxes the coil alignment tolerance. Protrusions are prevented because of the more efficient and uniform spacing of the coil to reduce heat buildup in the head during a write.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: July 11, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Daniel Wayne Bedell, Quang Le, Edward Hin Pong Lee, Son Van Nguyen, Vladimir Nikitin, Murali Ramasubramanian
  • Patent number: 7060638
    Abstract: A porous dielectric film for use in electronic devices is disclosed that is formed by removal of soluble nano phase porogens. A silicon based dielectric film having soluble porogens dispersed therein is prepared by chemical vapor deposition (CVD) or by spin on glass (S.O.G.). Examples of preferable porogens include compounds such as germanium oxide (GeO2) and boron oxide (B2O3). Hot water can be used in processing to wet etch the film, thereby removing the porogens and providing the porous dielectric film. The silicon based dielectric film may be a carbon doped silicon oxide in order to further reduce the dielectric constant of the film. Additionally, the porous dielectric film may be treated by an electron beam to enhance the electrical and mechanical properties of the film.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: June 13, 2006
    Assignee: Applied Materials
    Inventors: Son Van Nguyen, Hichem M'Saad, Bok Hoen Kim
  • Patent number: 7049247
    Abstract: A method for fabricating a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing a plasma enhanced chemical vapor deposition (“PECVD”) process is disclosed. Electronic devices containing insulating layers of thermally stable ultralow dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of a thermally stable ultralow dielectric constant film, specific precursor materials are used, such as, silane derivatives, for instance, diethoxymethylsilane (DEMS) and organic molecules, for instance, bicycloheptadiene and cyclopentene oxide.
    Type: Grant
    Filed: May 3, 2004
    Date of Patent: May 23, 2006
    Assignee: International Business Machines Corporation
    Inventors: Stephen M. Gates, Alfred Grill, David R. Medeiros, Deborah Neumayer, Son Van Nguyen, Vishnubhai V. Patel, Xinhui Wang
  • Patent number: 7043823
    Abstract: A current-perpendicular-to the-plane (CPP) magnetoresistive device, such as a magnetic tunnel junction (MTJ), is formed by patterning a capping layer (e.g., using resist) in the shape of a central region of an underlying free ferromagnetic layer that in turn resides over additional layers of the MTJ. Side regions of the capping layer are removed by ion milling or etching down into the free ferromagnetic layer. Unmasked side regions of the ferromagnetic layer are then oxidized to render them locally non-ferromagnetic and electrically insulating.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: May 16, 2006
    Inventors: Jeffrey R. Childress, Elizabeth A. Dobisz, Robert E. Fontana, Jr., Kuok San Ho, Ching Hwa Tsang, Son Van Nguyen
  • Patent number: 7031121
    Abstract: A perpendicular recording write head has ferromagnetic first and second pole pieces which are connected at a back gap and an insulation stack with a write coil layer embedded therein is located between the first and second pole pieces and between a head surface of the write head and the back gap. The second pole piece has a pole tip which is located at the head surface and a recessed ferromagnetic write shield layer. A nonmagnetic isolation layer is located between the second pole piece and the write shield layer and at least one ferromagnetic stud is magnetically connected between the first pole piece layer and the write shield layer and is located between the head surface and the insulation stack.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: April 18, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Gautam Khera, Quang Le, Son Van Nguyen, Aron Pentek, Mason Lamar Williams, III
  • Patent number: 7030468
    Abstract: Dielectric materials including elements of Si, C, O and H having specific values of mechanical properties (tensile stress, elastic modulus, hardness cohesive strength, crack velocity in water) that result in a stable ultra low k film which is not degraded by water vapor or integration processing are provided. The dielectric materials have a dielectric constant of about 2.8 or less, a tensile stress of less than 45 MPa, an elastic modulus from about 2 to about 15 GPa, and a hardness from about 0.2 to about 2 GPa. Electronic structures including the dielectric materials of the present invention as well as various methods of fabricating the dielectric materials are also provided.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: April 18, 2006
    Assignee: International Business Machines Corporation
    Inventors: Stephen M. Gates, Christos D. Dimitrakopoulos, Alfred Grill, Son Van Nguyen
  • Patent number: 7024756
    Abstract: The method of making a magnetic head assembly includes forming a second pole piece layer that is recessed from a head surface, forming a reactive ion etchable (RIEable) pole tip forming layer on the second pole piece layer, forming an adhesion/stop layer of tantalum (Ta) on the pole tip forming layer, forming a photoresist mask on the adhesion/stop layer with an opening for patterning the adhesion/stop layer and the pole tip forming layer with another opening, reactive ion etching (RIE) through the opening to form the other opening, forming the second pole piece pole tip in the other opening with a top which is above a top of the adhesion/stop layer and chemical mechanical polishing (CMP) the top of the second pole piece pole tip until the CMP contacts the adhesion/stop layer. The invention also includes the magnetic head made by such a process.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: April 11, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands, B.V.
    Inventors: Quang Le, Jui-lung Li, Jeffrey S. Lille, Son Van Nguyen
  • Patent number: 7022248
    Abstract: A method for patterning a self-aligned coil using a damascene process is disclosed. Coil pockets are formed in a first insulation layer disposed over a first pole layer. A barrier/seed layer is deposited along walls of the coil pockets in the insulation layer. Copper is formed in the coil pockets and over the insulation layer. The copper is planarized down to the insulation layer. The self-aligned coil process packs more copper into the same coil pocket and relaxes the coil alignment tolerance. Protrusions are prevented because of the more efficient and uniform spacing of the coil to reduce heat buildup in the head during a write.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: April 4, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Daniel Wayne Bedell, Quang Le, Edward Hin Pong Lee, Son Van Nguyen, Vladimir Nikitin, Murali Ramasubramanian
  • Patent number: 7011890
    Abstract: A method for depositing a low dielectric constant film is provided. The low dielectric constant film includes alternating sublayers, which include at least one carbon-doped silicon oxide sublayer. The sublayers are deposited by a plasma process than includes pulses of RF power. The alternating sublayers are deposited from two or more compounds that include at least one organosilicon compound. The two or more compounds and processing conditions are selected such that adjacent sublayers have different and improved mechanical properties.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: March 14, 2006
    Assignee: Applied Materials Inc.
    Inventors: Son Van Nguyen, Yi Zheng
  • Patent number: 6984579
    Abstract: A method for forming a conductive feature in a low k dielectric layer comprising a layer of nanotubes and a low k material between the nanotubes is provided. The low k dielectric layer may be deposited on a seed layer as a blanket layer that is patterned such that a conductive feature may be formed in the low k dielectric layer. Alternatively, the low k dielectric layer may be selectively deposited on a patterned seed layer between a sacrificial layer of a substrate. The sacrificial layer may be removed and replaced with conductive material to form a conductive feature in the low k dielectric layer.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: January 10, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Son Van Nguyen, Kang Sub Yim
  • Patent number: 6948231
    Abstract: The present invention presents a method for fabricating coil elements for magnetic write heads. A coil pattern is formed on a substrate using photolithographic techniques. The substrate is etched using reactive ion etching, creating a coil-shaped trench in the substrate. Thin film seed layers are deposited using ion beam deposition. The substrate is electroplated with metal filling the trenches with metal. The substrate is chemical mechanical polished to remove excess metal and planarize the air bearing surface of the write head.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: September 27, 2005
    Assignee: International Business Machines Corporation
    Inventors: Richard Hsiao, Quang Le, Paul P. Nguyen, Son Van Nguyen, Mustafa Pinarbasi, Patrick R. Webb, Howard G. Zolla
  • Patent number: 6919280
    Abstract: During manufacture, a magnetoresistive sensor having a ferromagnetic free layer is commonly provided with a tantalum cap layer. The tantalum cap layer provides protection to the sensor during manufacture and then is typically removed after performing annealing. The removal of the tantalum cap with a fluorine reactive ion etch leaves low volatility tantalum/fluorine byproducts. The present invention provides a method of using an argon/hydrogen reactive ion etch to remove the tantalum/fluorine byproducts. The resulting sensor has far less damage resulting from the presence of the fluorine byproducts.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: July 19, 2005
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Richard Hsiao, Wipul Pemsiri Jayasekara, Son Van Nguyen, Sue Zhang
  • Patent number: 6913992
    Abstract: Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: July 5, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Francimar Campana Schmitt, Li-Qun Xia, Son Van Nguyen, Shankar Venkataraman
  • Patent number: 6901653
    Abstract: A Damascene process is provided for manufacturing a coil structure for a magnetic head. During the manufacturing process, an insulating layer is initially deposited after which a photoresist layer is deposited. A silicon dielectric layer is then deposited on the photoresist layer. After masking the silicon dielectric layer, at least one channel is etched in the photoresist layer and the silicon dielectric layer. Then, a conductive seed layer is deposited in the at least one channel. The at least one channel is then ready to be filled with a conductive material and chemically/mechanically polished to define a coil structure.
    Type: Grant
    Filed: April 2, 2002
    Date of Patent: June 7, 2005
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Richard Hsiao, Prakash Kasiraj, Quang Le, Paul Phong Nguyen, Son Van Nguyen, Denny D. Tang, Patrick Rush Webb
  • Patent number: 6878620
    Abstract: Methods and apparatus for protecting the dielectric layer sidewalls of openings, such as vias and trenches, in semiconductor substrates are provided. A pre-liner and a liner are deposited over the sidewalls of the openings as part of integrated processing sequences that either do not remove the photoresist until subsequent processing or remove the photoresist with a plasma etch that does not contaminate the sidewalls of the openings.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: April 12, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Son Van Nguyen, Li-Qun Xia, Srinivas D. Nemani
  • Publication number: 20040223267
    Abstract: A current-perpendicular-to the-plane (CPP) magnetoresistive device has two ferromagnetic layers separated by a nonmagnetic spacer layer with the free ferromagnetic layer having a central region of ferromagnetic material and nonmagnetic side regions formed of one or more oxides of the ferromagnetic material. One type of CPP device is a magnetic tunnel junction (MTJ) magnetoresistive read head in which the lower pinned layer has a width and height greater than the width and height, respectively, of the overlying central region of the upper free layer, with the side regions of the free layer being oxidized and therefore nonmagnetic. The MTJ read head is formed by patterning resist in the shape of the free layer central region over the stack of layers in the MTJ, ion milling or etching the stack down into the free layer, and then exposing the stack to oxygen to oxidize the ferromagnetic material in the side regions not covered by the resist.
    Type: Application
    Filed: June 15, 2004
    Publication date: November 11, 2004
    Inventors: Jeffrey R. Childress, Elizabeth A. Dobisz, Robert E. Fontana, Kuok San Ho, Ching Hwa Tsang, Son Van Nguyen