Abstract: In order to avoid a faulty pattern resulting from a photoresist tail being formed due to a step difference of an upper hard mask layer when a dual hard mask layer is used, a planarization layer is formed following patterning of the upper hard mask layer. In this manner, a photoresist pattern is formed without the creation of a photoresist tail. Alternatively, a single hard mask layer and a planarization layer are substituted for the dual lower hard mask layer and an upper hard mask layer, respectively. In this manner, it is therefore possible to form a photoresist pattern without a photoresist tail being formed during photolithographic processes. In order to prevent formation of a facet, the planarization layer is thickly formed or, alternatively, the hard mask layer is etched using the photoresist pattern.

Abstract: A method for forming a metal interconnection layer of a semiconductor device comprises forming a film including a material selective to a medium used in an ashing process on an interlayer insulating film. The method comprises transforming the film during the ashing process to form an interconnection pattern having a dual damascene structure. A dielectric material such as copper is deposited on the interconnection pattern, which is planarized through CMP, thereby forming a via contact having a single damascene structure without a recess therein.

Abstract: Disclosed is a method of patterning inter-metal dielectric layers. The method comprises a) sequentially layering a lower etch-stop layer, a lower dielectric layer, an upper etch-stop layer, and an upper dielectric layer on a semiconductor substrate including a lower circuit patterned thereon, b) patterning the upper dielectric layer, the upper etch-stop layer, and the lower dielectric layer to form a via hole to expose the lower etch-stop layer on the lower circuit, c) irradiating UV rays to the via hole, d) forming a photoresist layer on the resulting semiconductor substrate including the via hole thereon, and patterning the photoresist layer, e) patterning the upper dielectric layer using the patterned photoresist layer as an etching mask to form a metal circuit around the via hole in the upper dielectric layer, and f) exposing an upper portion of the lower circuit.

Abstract: In a method for forming a dual damascene wiring pattern, an etch stop film and an interlayer dielectric film comprising an SiOC:H group material are formed on a substrate having an electrical connection layer formed thereon. An anti-reflection layer Is formed on the interlayer dielectric film. A primary opening s formed by etching the anti-reflection layer and the interlayer dielectric film to expose a surface of the etch stop film. A sacrificial film is formed comprising a low dielectric constant material in the primary opening and on the anti-reflection layer. A trench photoresist pattern having a width larger than that of the primary opening is formed on the sacrificial film after plasma-processing the sacrificial film.

Abstract: Provided are an inter-metal dielectric pattern and a method of forming the same. The pattern includes a lower interconnection disposed on a semiconductor substrate, a lower dielectric layer having a via hole exposing the lower interconnection and covering the semiconductor substrate where the lower interconnection is disposed, and an upper dielectric pattern and a lower capping pattern, which include a trench line exposing the via hole and sequentially stacked on the lower dielectric layer. The lower dielectric layer and the upper dielectric pattern are low k-dielectric layers formed of materials such as SiO2, SiOF, SiOC, and porous dielectric. The method includes forming an inter-metal dielectric layer including a lower dielectric layer and upper dielectric layer, which are sequentially stacked, on a lower interconnection formed on a semiconductor substrate. The inter-metal dielectric layer is patterned to form a via hole, which exposes the upper side of the lower interconnection.

Abstract: Methods for forming a metal wiring layer in a semiconductor device using a dual damascene process.

Abstract: A method for forming a metal wiring layer in a semiconductor device using a dual damascene process is provided. A stopper layer, an interlayer insulating layer, and a hard mask layer are sequentially formed on a semiconductor substrate having a conductive layer. A first photoresist pattern that comprises a first opening having a first width is formed on the hard mask layer. The hard mask layer and portions of the interlayer insulating layer are etched using the first photoresist pattern as an etching mask, thereby forming a partial via hole having the first width. The first photoresist pattern is removed. An organic material layer is coated on the semiconductor substrate having the partial via hole is formed to fill the partial via hole with the organic material layer. A second photoresist pattern that comprises a second opening aligned with the partial via hole and having a second width greater than the first width is formed on the coated semiconductor substrate.

Abstract: A method of forming an interconnection line in a semiconductor device is provided. A first etching stopper is formed on a lower conductive layer which is formed on a semiconductor substrate. A first interlayer insulating layer is formed on the first etching stopper. A second etching stopper is formed on the first interlayer insulating layer. A second interlayer insulating layer is formed on the second etching stopper. The second interlayer insulating layer, the second etching stopper, and the first interlayer insulating layer are sequentially etched using the first etching stopper as an etching stopping point to form a via hole aligned with the lower conductive layer. A protective layer is formed to protect a portion of the first etching stopper exposed at the bottom of the via hole. A portion of the second interlayer insulating layer adjacent to the via hole is etched using the second etching stopper as an etching stopping point to form a trench connected to the via hole. The protective layer is removed.

Abstract: A method of fabricating a semiconductor device having a low dielectric constant is disclosed. According to the method, a silicon oxycarbide layer is formed, treated with plasma, and patterned. The silicon oxycarbide layer is formed by a coating method or a CVD method such as a PECVD method. Treating the silicon oxycarbide layer with plasma is performed by supplying at least one gas selected from a group of He, H2, N2O, NH3, N2, O2 and Ar. It is desirable that plasma be applied at the silicon oxycarbide layer in a PECVD device by an in situ method after forming the silicon oxycarbide layer. In a case in which a capping layer is further stacked and patterned, it is desirable to treat with H2-plasma. Even in a case in which an interlayer insulation is formed of the silicon oxycarbide layer and a coating layer of an organic polymer group for a dual damascene process, it is desirable to perform the plasma treatment before forming the coating layer.

Abstract: Disclosed is a method for forming interconnection lines using a hydrosilsesquioxane (HSQ) layer as an interlayer insulating layer. A HSQ layer is formed over a semiconductor substrate and an entire surface of the HSQ layer is subjected to plasma treatment. It is then possible to pattern the HSQ layer using photo etching, for the bond structure density of an upper part of the HSQ layer has been increased due to the plasma treatment. An opening is formed by patterning the treated HSQ layer and then a conductive layer filling the opening is formed. In this manner, a multilayer interconnection structure can be formed with a low dielectric layer made of HSQ, thereby reducing the resistance-capacitance (RC) delay.

Abstract: There is provided a semiconductor device fabrication method. In the method, a gate layer is formed on a semiconductor substrate and patterned to form a first resultant structure, a metal layer is formed on the first resultant structure, a capping layer is formed on the metal layer, a metal silicide is formed on the gate layer by heating the substrate at a first temperature, unreacted metal layer and first capping layer are removed to form a second resultant structure, a second capping layer is formed on the second resultant structure, and the substrate is heated at a second temperature higher than the first temperature. The second capping layer suppresses a silicidation rate in the secondary heat treatment, thereby allowing a silicide of a good morphology to be achieved.

Abstract: A method of fabricating a semiconductor device employing a multi-layer metal interconnect structure that has a copper (Cu) interconnection layer. Low-temperature plasma processing is first performed on the surface of the Cu interconnection layer, an insulation layer is deposited on the plasma-processed Cu interconnection layer, and the resultant structure is thermally treated.

Abstract: A semiconductor device fabricating method and apparatus for filling gaps between patterns by use of high density plasma oxide films, wherein, a first high density plasma oxide film is deposited on a semiconductor substrate that has patterns with a gap formed thereon and then etched to a predetermined depth using fluorine ions. A second high density plasma oxide film is deposited on the resultant structure, thereby filling the gap between the patterns.

Abstract: The present invention relates to a material for hydrogen-storage constituted by Ti-Mn alloy system which has a high hydrogen-storage capacity, plateau hydrogen dissociation equilibrium pressure, hypostoichiometric composition and crystal structure of C14. Ti-Mn alloy system for hydrogen-storage of the invention which has a C14 crystal structure, is represented as: Ti.sub.u Zr.sub.v Mn.sub.w Cr.sub.x V.sub.y X.sub.z, wherein, X is at least one of element selected from the group consisting of Fe, Al and Ni; u, v, w, x, y and z are mole numbers of each components; 0.7<u<1.0; 0<v<0.3; 1.0.ltoreq.w.ltoreq.1.3; 0.1.ltoreq.x.ltoreq.0.4; 0<y<0.3; 0.ltoreq.z.ltoreq.0.2; 0.7<u+v<1.0; 1.4.ltoreq.w+x.ltoreq.1.7; and, 1.3.ltoreq.w+x+y+z<2.0.

Abstract: The present invention relates to a process for preparing an electrode for secondary battery employing hydrogen-storage alloy systems, more specifically, to a process for preparing an anode material for secondary battery which can be charged/discharged in an electrolyte and has a high discharge efficiency and energy density per unit weight, by sintering a mixture of hydrogen-storage alloy systems. An electrode for secondary battery of the present invention is prepared by the process which comprises the steps of: (i) mixing a hydrogen-storage alloy powder free of Ni with a hydrogen-storage alloy powder containing Ni over 30 atomic %; (ii) cold-pressing the mixed powder at a pressure of 5 to 15 ton/cm.sup.2 ; (iii) sintering the cold-pressed mixture in a quartz tube at 900.degree. C. for 5 to 15 min under a vacuum condition of 10.sup.-2 to 10.sup.-3 torr; and, (iv) quenching the sintered material.