Patents by Inventor Sreenivasan K. Koduri

Sreenivasan K. Koduri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200168531
    Abstract: A packaged semiconductor device includes a semiconductor die mounted on a leadframe, a housing for the semiconductor die defining a horizontal plane and a horizontal direction. The leadframe includes leads each having an inner lead portion inside the housing and an outer lead portion that includes a first portion that extends out in the horizontal direction from one of the sidewalls of the housing, a transition portion that includes a vertical direction component, and a distal end portion, wherein the distal end portion of the leads are all on the horizontal plane. The outer lead portions alternate between a gull wing lead shape having the distal end portions extending in the horizontal direction outward from the housing and inward extending leads that have their distal end portions extending in the horizontal direction inward toward the housing. The leadframe consists of a single leadframe.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 28, 2020
    Inventors: MICHAEL L. MEYERS, SCOTT F. EISENHART, RICHARD J. SAYE, SREENIVASAN K. KODURI
  • Patent number: 10658278
    Abstract: In described examples, a terminal (e.g., a conductive terminal) includes a base material, a plating stack and a solder finish. The base material can be a metal, such as copper. The plating stack is arranged on a surface of the base material, and includes breaks in the plating stack. The breaks in the plating stack extend from a first surface of the plating stack to a second surface of the plating stack adjacent to the surface of the base material. The solder finish is coated over the breaks in the plating stack.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: May 19, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sreenivasan K Koduri
  • Publication number: 20200144358
    Abstract: A microelectronic device has bump bonds and an inductor on a die. The microelectronic device includes first lateral conductors extending along a terminal surface of the die, wherein at least some of the first lateral conductors contact at least some of terminals of the die. The microelectronic device also includes conductive columns on the first lateral conductors, extending perpendicularly from the terminal surface, and second lateral conductors on the conductive columns, opposite from the first lateral conductors, extending laterally in a plane parallel to the terminal surface. A first set of the first lateral conductors, the conductive columns, and the second lateral conductors provide the bump bonds of the microelectronic device. A second set of the first lateral conductors, the conductive columns, and the second lateral conductors are electrically coupled in series to form the inductor. Methods of forming the microelectronic device are also disclosed.
    Type: Application
    Filed: November 6, 2018
    Publication date: May 7, 2020
    Applicant: Texas Instruments Incorporated
    Inventor: Sreenivasan K. Koduri
  • Patent number: 10643929
    Abstract: A coupling device provides galvanic isolation using a leadframe that is configured to support two integrated circuit chips in a coplanar manner. Each chip contains an inductive coupling coil. The lead frame includes a set of bond pads for attaching bond wires to couple to the two integrated circuit chips. Two separated die attach pads support the two chips. Each die attach pad is configured to support one of the two integrated circuit chips with a plurality of cantilevered fingers.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: May 5, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Michael Sutton, Sreenivasan K Koduri, Subhashish Mukherjee
  • Patent number: 10636758
    Abstract: A microelectronic device has a bump bond structure including an electrically conductive pillar with an expanded head, and solder on the expanded head. The electrically conductive pillar includes a column extending from an I/O pad to the expanded head. The expanded head extends laterally past the column on at least one side of the electrically conductive pillar. In one aspect, the expanded head may have a rounded side profile with a radius approximately equal to a thickness of the expanded head, and a flat top surface. In another aspect, the expanded head may extend past the column by different lateral distances in different lateral directions. In a further aspect, the expanded head may have two connection areas for making electrical connections to two separate nodes. Methods for forming the microelectronic device are disclosed.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: April 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sreenivasan K Koduri
  • Patent number: 10330537
    Abstract: A method of manufacturing a thermometer probe includes: obtaining a hollow housing having an open end and a curved inner surface; obtaining a flexible detecting component having an adhesive layer; obtaining an insertion component; detachably attaching the flexible detecting component to the insertion component; inserting the insertion component, having the flexible detecting component attached thereto, through the open end of the hollow housing and into the hollow housing such that the adhesive layer is disposed between the insertion component and the inner surface; and adhering, via the adhesive layer, the flexible detecting component to the curved inner surface.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: June 25, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Sreenivasan K Koduri
  • Publication number: 20190109016
    Abstract: In one instance, a method of forming a semiconductor package with a leadframe includes cutting, such as with a laser, a first side of a metal strip to a depth D1 according to a cutting pattern to form a first plurality of openings, which may be curvilinear. The method further includes etching the second side of the metal strip to a depth D2 according to a photoresist pattern to form a second plurality of openings. At least some of the first plurality of openings are in fluid communication with at least some of the second plurality of openings to form a plurality of leadframe leads. The depth D1 is shallower than a height H of the metal strip, and the depth D2 is also shallower than the height H. Other embodiments are presented.
    Type: Application
    Filed: October 3, 2018
    Publication date: April 11, 2019
    Inventor: Sreenivasan K. Koduri
  • Publication number: 20190109105
    Abstract: A semiconductor packaging structure includes a die including a bond pad and a first metal layer structure disposed on the die, the first metal layer structure having a first width, the first metal layer structure including a first metal layer, the first metal layer electrically coupled to the bond pad. The semiconductor packaging structure also includes a first photosensitive material around sides of the first metal layer structure and a second metal layer structure disposed over the first metal layer structure and over a portion of the first photosensitive material, the second metal layer structure electrically coupled to the first metal layer structure, the second metal layer structure having a second width, where the second width is greater than the first width. Additionally, the semiconductor packaging structure includes a second photosensitive material around sides of the second metal layer structure.
    Type: Application
    Filed: October 1, 2018
    Publication date: April 11, 2019
    Inventor: Sreenivasan K. Koduri
  • Publication number: 20190109110
    Abstract: In one instance, a semiconductor package includes a lead frame and a semiconductor die mounted to the lead frame via a plurality of bumps that are shaped or tapered. Each of the plurality of bumps includes a first end connected to the semiconductor die and an opposing, second end connected to the lead frame. The first end has an end surface area A1. The second end has an end surface area A2. The end surface area A1 of the first end is less than the end surface area A2 of the second end. Other aspects are disclosed.
    Type: Application
    Filed: August 14, 2018
    Publication date: April 11, 2019
    Inventor: Sreenivasan K. Koduri
  • Publication number: 20190109076
    Abstract: In one instance, a semiconductor package includes a metal leadframe having a first plurality of openings extending partially into the leadframe from the first side and a second plurality of openings extending partially into the leadframe from the second side together forming a plurality of leads. A pre-mold compound is positioned in the second plurality of openings that at least partially supports the plurality of leads. The seminconductor package has a plurality of bumps extending from the landing sites to a semiconductor die and a molding compounding at least partially covering the plurality of bumps and the metal leadframe. Other packages and methods are disclosed.
    Type: Application
    Filed: October 3, 2018
    Publication date: April 11, 2019
    Inventor: Sreenivasan K. Koduri
  • Publication number: 20190109108
    Abstract: A microelectronic device has a bump bond structure including an electrically conductive pillar with an expanded head, and solder on the expanded head. The electrically conductive pillar includes a column extending from an I/O pad to the expanded head. The expanded head extends laterally past the column on at least one side of the electrically conductive pillar. In one aspect, the expanded head may have a rounded side profile with a radius approximately equal to a thickness of the expanded head, and a flat top surface. In another aspect, the expanded head may extend past the column by different lateral distances in different lateral directions. In a further aspect, the expanded head may have two connection areas for making electrical connections to two separate nodes. Methods for forming the microelectronic device are disclosed.
    Type: Application
    Filed: July 9, 2018
    Publication date: April 11, 2019
    Applicant: Texas Instruments Incorporated
    Inventor: Sreenivasan K Koduri
  • Publication number: 20190109093
    Abstract: A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.
    Type: Application
    Filed: July 23, 2018
    Publication date: April 11, 2019
    Applicant: Texas Instruments Incorporated
    Inventor: Sreenivasan K Koduri
  • Publication number: 20180323361
    Abstract: A circuit board includes an embedded thermoelectric device with hard thermal bonds. A method includes embedding a thermoelectric device in a circuit board and forming hard thermal bonds.
    Type: Application
    Filed: July 10, 2018
    Publication date: November 8, 2018
    Inventors: Henry L. Edwards, Kenneth J. Maggio, Steven Kummerl, Sreenivasan K. Koduri
  • Publication number: 20180301402
    Abstract: A semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and a passive component electrically connected to the semiconductor die through the leadframe. The leadframe includes a cavity in which at least a portion of the passive component is disposed in a stacked arrangement.
    Type: Application
    Filed: April 11, 2018
    Publication date: October 18, 2018
    Inventors: Jeffrey MORRONI, Rajeev Dinkar JOSHI, Sreenivasan K. KODURI, Sujan Kundapur MANOHAR, Yogesh K. RAMADASS, Anindya PODDAR
  • Publication number: 20180301404
    Abstract: A semiconductor package includes a leadframe and a semiconductor die attached to the leadframe by way of solder posts. In a stacked arrangement, the package also includes a passive component disposed between the leadframe and the semiconductor die and electrically connected to the semiconductor die through the leadframe.
    Type: Application
    Filed: April 11, 2018
    Publication date: October 18, 2018
    Inventors: Jeffrey MORRONI, Rajeev Dinkar JOSHI, Sreenivasan K. KODURI, Sujan Kundapur MANOHAR, Yogesh K. RAMADASS, Anindya PODDAR
  • Publication number: 20180301403
    Abstract: A semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and a passive component electrically connected to the semiconductor die through the leadframe. The leadframe includes a cavity in a side of the leadframe opposite the semiconductor die, and at least a portion of the passive component resides within the cavity in a stacked arrangement.
    Type: Application
    Filed: April 11, 2018
    Publication date: October 18, 2018
    Inventors: Jeffrey MORRONI, Rajeev Dinkar JOSHI, Sreenivasan K. KODURI, Sujan Kundapur MANOHAR, Yogesh K. RAMADASS, Anindya PODDAR
  • Patent number: 9899339
    Abstract: A method of making an electronic device having a discrete device mounted on a surface of an electronic die with both the discrete device and the die connected by heat cured conductive ink and covered with cured encapsulant including placing the discrete device on the die; and keeping the temperature of each of the discrete device and the die below about 200° C. Also disclosed is a method of electrically attaching a discrete device to a substrate that includes placing the device on the substrate, applying conductive ink that connects at least one terminal on the device to at least one contact on the substrate and curing the conductive ink. Also disclosed is an IC package with a discrete electrical device having electrical terminals; an electrical substrate having contact pads on a surface thereof; and cured conductive ink connecting at least one of the electrical terminals with at least one of the contact pads.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: February 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Matthew David Romig, Lance Cole Wright, Leslie Edward Stark, Frank Stepniak, Sreenivasan K. Koduri
  • Publication number: 20170227403
    Abstract: A method of manufacturing a thermometer probe includes: obtaining a hollow housing having an open end and a curved inner surface; obtaining a flexible detecting component having an adhesive layer; obtaining an insertion component; detachably attaching the flexible detecting component to the insertion component; inserting the insertion component, having the flexible detecting component attached thereto, through the open end of the hollow housing and into the hollow housing such that the adhesive layer is disposed between the insertion component and the inner surface; and adhering, via the adhesive layer, the flexible detecting component to the curved inner surface.
    Type: Application
    Filed: April 24, 2017
    Publication date: August 10, 2017
    Inventor: Sreenivasan K. Koduri
  • Patent number: 9664574
    Abstract: A method of manufacturing a thermometer probe includes: obtaining a hollow housing having an open end and a curved inner surface; obtaining a flexible detecting component having an adhesive layer; obtaining an insertion component; detachably attaching the flexible detecting component to the insertion component; inserting the insertion component, having the flexible detecting component attached thereto, through the open end of the hollow housing and into the hollow housing such that the adhesive layer is disposed between the insertion component and the inner surface; and adhering, via the adhesive layer, the flexible detecting component to the curved inner surface.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: May 30, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sreenivasan K Koduri
  • Patent number: 9354186
    Abstract: An apparatus having an X-ray sensor assembly with X-ray blocking pixels divided by X-ray transmitting gaps with the X-ray blocking pixels casting an X-ray blocking shadow; and a die containing signal processing electronics, with the signal processing electronics positioned substantially entirely within the X-ray blocking shadow. A method for detecting the alignment between the X-ray sensor assembly and the die is disclosed. Also disclosed is an X-ray computed tomography machine having a printed circuit board (“PCB”), a die embedded in the PCB, and a signal source wherein signals are routed to and from the die by traces on at least one of the surfaces of the PCB.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: May 31, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Eduardo Bartolome, Sreenivasan K. Koduri