Patents by Inventor Srinivas Devadas

Srinivas Devadas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9628272
    Abstract: Mechanisms for operating a prover device and a verifier device so that the verifier device can verify the authenticity of the prover device. The prover device generates a data string by: (a) submitting a challenge to a physical unclonable function (PUF) to obtain a response string, (b) selecting a substring from the response string, (c) injecting the selected substring into the data string, and (d) injecting random bits into bit positions of the data string not assigned to the selected substring. The verifier: (e) generates an estimated response string by evaluating a computational model of the PUF based on the challenge; (f) performs a search process to identify the selected substring within the data string using the estimated response string; and (g) determines whether the prover device is authentic based on a measure of similarity between the identified substring and a corresponding substring of the estimated response string.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: April 18, 2017
    Assignees: WILLIAM MARSH RICE UNIVERSITY, MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Masoud Rostami, Mehrdad Majzoobi, Farinaz Koushanfar, Daniel S. Wallach, Srinivas Devadas
  • Publication number: 20160070712
    Abstract: A first search is executed to obtain a first set of search results corresponding to a first geographical search area. A determination is made that the first set of search results does not meet a search results criteria. A second geographical search region is dynamically selected for executing a second search in response to determining that the first set of search results does not meet the search results criteria. The second search is executed to obtain a second set of search results corresponding to the second geographical search area.
    Type: Application
    Filed: October 22, 2014
    Publication date: March 10, 2016
    Inventors: Swetha Prabhakar, Krishna Prabhakar, Srinivas Devadas
  • Publication number: 20150195088
    Abstract: Mechanisms for operating a prover device and a verifier device so that the verifier device can verify the authenticity of the prover device. The prover device generates a data string by: (a) submitting a challenge to a physical unclonable function (PUF) to obtain a response string, (b) selecting a substring from the response string, (c) injecting the selected substring into the data string, and (d) injecting random bits into bit positions of the data string not assigned to the selected substring. The verifier: (e) generates an estimated response string by evaluating a computational model of the PUF based on the challenge; (f) performs a search process to identify the selected substring within the data string using the estimated response string; and (g) determines whether the prover device is authentic based on a measure of similarity between the identified substring and a corresponding substring of the estimated response string.
    Type: Application
    Filed: January 3, 2014
    Publication date: July 9, 2015
    Applicant: WILLIAM MARSH RICE UNIVERSITY
    Inventors: Masoud Rostami, Mehrdad Majzoobi, Farinaz Koushanfar, Daniel S. Wallach, Srinivas Devadas
  • Publication number: 20150026545
    Abstract: A method and system are provided for a symbol-oriented approach that addresses information recovery from manufacturing variations (MVs) readings in a high noise environment. The multi-bits-per-symbol approach, which is in accordance with the various aspects of the present invention, is in contrast with how manufacturing-variation-derived bits are normally treated in the context of PUF Key Generation's error correction process. The multi-bit-per-symbol approach also offers a natural distance metric (distance to the most-likely symbol, distance to the next-most-likely symbol, etc.) which can aid soft-decision decoding or list-decoding, and can be used to improve the provisioning of a more reliably encoded secret and its associated helper data value.
    Type: Application
    Filed: July 18, 2014
    Publication date: January 22, 2015
    Inventors: Meng-Day Mandel YU, Srinivas DEVADAS
  • Patent number: 8904154
    Abstract: An execution migration approach includes bringing the computation to the locus of the data: when a memory instruction requests an address not cached by the current core, the execution context (current program counter, register values, etc.) moves to the core where the data is cached.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: December 2, 2014
    Assignee: Massachusetts Institute of Technology
    Inventors: Srinivas Devadas, Omer Khan, Mieszko Lis, Keun Sup Shim, Myong Hyon Cho
  • Patent number: 8811615
    Abstract: Outputs from at least one pseudo-random source are used to encode hidden value. The hidden value is encoded using index based quantities, for example, based on numerically ordering a sequence of outputs from pseudo-random source(s). In some examples, the numerical ordering of re-generated device-specific quantities is used to re-generate the hidden value, without necessarily requiring additional error correction mechanisms. Information leak may be reduced by constructing system whose “syndrome” helper bits are random, as measured, for example, by NIST's Statistical Tests for Randomness In some examples, index based coding provides coding gain that exponentially reduces total error correction code complexity, resulting in efficiently realizable PRS-based key generation systems. In some examples, index based coding allows noisy PRS to be robust across conditions where conventional error correction code cannot error correct.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: August 19, 2014
    Assignee: Verayo, Inc.
    Inventors: Meng-Day Yu, Srinivas Devadas
  • Patent number: 8782396
    Abstract: Physical Unclonable Functions (PUFs) for authentication can be implemented in a variety of electronic devices including FPGAs, RFIDs, and ASICs. In some implementations, challenge-response pairs corresponding to individual PUFs can be enrolled and used to determine authentication data, which may be managed in a database. Later when a target object with a PUF is intended to be authenticated a set (or subset) of challenges are applied to each PUF device to authenticate it and thus distinguish it from others. In some examples, authentication is achieved without requiring complex cryptography circuitry implemented on the device. Furthermore, an authentication station does not necessarily have to be in communication with an authority holding the authentication data when a particular device is to be authenticated.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: July 15, 2014
    Assignee: Verayo, Inc.
    Inventors: Thomas Ziola, Zdenek Paral, Srinivas Devadas, Gookwon Edward Suh, Vivek Khandelwal
  • Patent number: 8762723
    Abstract: An approach to cryptographic security uses a “fuzzy” credential, in contrast to a “hard” credential, to eliminate cryptographic algorithmic repeatability on a device that may be subject to physical attacks. By eliminating repeatability performed at an algorithmic (e.g., gate or software) level, a device inherently lacks one of the fundamental setup assumptions associated with certain classes of side channel, fault injection, timing, and related attacks, thus helps to protect the system against such attacks while preserving the cryptographic security of the system.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: June 24, 2014
    Assignee: Verayo, Inc.
    Inventors: Meng-Day Yu, Srinivas Devadas, David M'Raihi, Eric Duprat
  • Patent number: 8756438
    Abstract: A field configurable device, such as an FPGA, supports secure field configuration without using non-volatile storage for cryptographic keys on the device and without requiring a continuous or ongoing power source to maintain a volatile storage on the device. The approach can be used to secure the configuration data such that it can in general be used on a single or a selected set of devices and/or encryption of the configuration data so that the encrypted configuration data can be exposed without compromising information encoded in the configuration data.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: June 17, 2014
    Assignee: Verayo, Inc.
    Inventors: Srinivas Devadas, Thomas J. Ziola
  • Patent number: 8683210
    Abstract: An integrated circuit includes a sequence generator configured to generate a series of challenges; a hidden output generator configured to generate a series of hidden outputs, each hidden output a function of a corresponding challenge in the series of challenges; and bit reduction circuitry configured to generate a response sequence including a plurality of response parts, each response part a function of a corresponding plurality of hidden outputs.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: March 25, 2014
    Assignee: Verayo, Inc.
    Inventor: Srinivas Devadas
  • Patent number: 8667283
    Abstract: A message is signed using a PUF without having to exactly regenerate a cryptographic key. Another party that shares information about the PUF is able to verify the signature to a high degree of accuracy (i.e., high probability of rejection of a forged signature and a low probably of false rejection of a true signature). In some examples, the information shared by a recipient of a message signature includes a parametric model of operational characteristics of the PUF used to form the signature.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: March 4, 2014
    Assignee: Verayo, Inc.
    Inventors: William Henry Bares, Srinivas Devadas, Vivek Khandelwal, Zdenek Paral, Richard Sowell, Tonghang Zhou
  • Patent number: 8630410
    Abstract: Subsets of multiple signal generator circuits embodied in a device are selected, and then a volatile value for the device is generated from the selected subsets. The volatile value may be used for authentication of the device and/or for cryptographic procedures performed on the device. The signal generator circuits may each comprise an oscillator circuit, and the selection of the subsets may be according to a comparison of the outputs of the subsets of circuits, for example, according to a comparison of output oscillation frequencies.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: January 14, 2014
    Assignee: Verayo, Inc.
    Inventors: Gookwon Edward Suh, Srinivas Devadas
  • Publication number: 20130298211
    Abstract: The disclosed invention is a system and method that allows for authentication of a user to a network using a token. The token interacts with a device and authenticates the user to the system. The token may be part of the device or stand alone. The various aspects of the present invention capture a novel design for an authentication token that eliminates the need for user interaction with the token.
    Type: Application
    Filed: April 2, 2013
    Publication date: November 7, 2013
    Applicant: VERAYO, INC.
    Inventors: David M'Raihi, Srinivas Devadas, WILLIAM HENRY BARES, Meng-Day Mandel Yu, ZDENEK SIDNEY PARAL
  • Patent number: 8386801
    Abstract: A group of devices are fabricated based on a common design, each device having a corresponding plurality of measurable characteristics that is unique in the group to that device, each device having a measurement module for measuring the measurable characteristics. Authentication of one of the group of devices is enabled by selective measurement of one or more of the plurality of measurable characteristics of the device.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: February 26, 2013
    Assignee: Massachusetts Institute of Technology
    Inventors: Srinivas Devadas, Blaise Gassend
  • Publication number: 20130010957
    Abstract: An approach to cryptographic security uses a “fuzzy” credential, in contrast to a “hard” credential, to eliminate cryptographic algorithmic repeatability on a device that may be subject to physical attacks. By eliminating repeatability performed at an algorithmic (e.g., gate or software) level, a device inherently lacks one of the fundamental setup assumptions associated with certain classes of side channel, fault injection, timing, and related attacks, thus helps to protect the system against such attacks while preserving the cryptographic security of the system.
    Type: Application
    Filed: July 6, 2012
    Publication date: January 10, 2013
    Applicant: Verayo, Inc.
    Inventors: Meng-Day Yu, Srinivas Devadas, David M'Raihi, Eric Duprat
  • Publication number: 20120301433
    Abstract: The present invention generally relates to engineered bacteriophages which express amyloid peptides for the modulation (e.g. increase or decrease) of protein aggregates and amyloid formation. In some embodiments, the engineered bacteriophages express anti-amyloid peptides for inhibiting protein aggregation and amyloid formation, which can be useful in the treatment and prevention of and bacterial infections and biofilms. In some embodiments, the engineered bacteriophages express amyloid peptides for promoting amyloid formation, which are useful for increasing amyloid formation such as promoting bacterial biofilms. Other aspects relate to methods to inhibit bacteria biofilms, and methods for the treatment of amyloid related disorders, e.g., Alzheimer's disease using an anti-amyloid peptide engineered bacteriophages. Other aspects of the invention relate to engineered bacteriophages to express the amyloid peptides on the bacteriophage surface and/or secrete the amyloid peptides, e.g.
    Type: Application
    Filed: July 29, 2010
    Publication date: November 29, 2012
    Applicants: WHITEHEAD INSTITUTE FOR BIOMEDICAL RESEARCH, MASSACHUSETTS INSTITUTE OF TECHNOLOGY, TRUSTEES OF BOSTON UNIVERSITY
    Inventors: Timothy Kuan-Ta Lu, Susan Lindquist, Rajaraman Krishnan, James Collins, Charles W. O'Donnell, Bonnie Berger Leighton, Srinivas Devadas
  • Publication number: 20120290845
    Abstract: A message is signed using a PUF without having to exactly regenerate a cryptographic key. Another party that shares information about the PUF is able to verify the signature to a high degree of accuracy (i.e., high probability of rejection of a forged signature and a low probably of false rejection of a true signature). In some examples, the information shared by a recipient of a message signature includes a parametric model of operational characteristics of the PUF used to form the signature.
    Type: Application
    Filed: May 9, 2011
    Publication date: November 15, 2012
    Applicant: Verayo, Inc.
    Inventors: William Henry Bares, Srinivas Devadas, Vivek Khandelwal, Zdenek Paral, Richard Sowell, Tonghang Zhou
  • Publication number: 20120183135
    Abstract: A method is used to reliably provision and re-generate a finite and exact sequence of bits, for use with cryptographic applications, e.g., as a key, by employing one or more challengeable Physical Unclonable Function (PUF) circuit elements. The method reverses the conventional paradigm of using public challenges to generate secret PUF responses; it exposes the response and keeps the particular challenges that generate the response secret.
    Type: Application
    Filed: January 19, 2011
    Publication date: July 19, 2012
    Applicant: Verayo, Inc.
    Inventors: Zdenek Paral, Srinivas Devadas
  • Publication number: 20120033810
    Abstract: A group of devices are fabricated based on a common design, each device having a corresponding plurality of measurable characteristics that is unique in the group to that device, each device having a measurement module for measuring the measurable characteristics. Authentication of one of the group of devices is enabled by selective measurement of one or more of the plurality of measurable characteristics of the device.
    Type: Application
    Filed: March 3, 2011
    Publication date: February 9, 2012
    Applicant: Massachusetts Institute of Technology
    Inventors: Srinivas Devadas, Blaise Gassend
  • Publication number: 20110258420
    Abstract: An execution migration approach includes bringing the computation to the locus of the data: when a memory instruction requests an address not cached by the current core, the execution context (current program counter, register values, etc.) moves to the core where the data is cached.
    Type: Application
    Filed: April 15, 2011
    Publication date: October 20, 2011
    Applicant: Massachusetts Institute of Technology
    Inventors: Srinivas Devadas, Omer Khan, Mieszko Lis, Keun Sup Shim, Myong Hyon Cho