Abstract: A digital value is generated in an integrated circuit such that the generated value substantially depends on circuit parameters that vary among like devices. The generated digital value is then used, for example, to access protected information in the device or to perform a cryptographic function in the integrated circuit.

Abstract: An integrated circuit has a first component that has a dynamic characteristic that varies among like integrated circuits, for example, among integrated circuits fabricated using the same lithography mask. Operating the first component produces an output that is dependent on the dynamic characteristic of the first component. A digital value associated with the integrated circuit is generated using the output of the first component, and then the generated digital value is used in operation of the integrated circuit.

Abstract: A field configurable device, such as an FPGA, supports secure field configuration without using non-volatile storage for cryptographic keys on the device and without requiring a continuous or ongoing power source to maintain a volatile storage on the device. The approach can be used to secure the configuration data such that it can in general be used on a single or a selected set of devices and/or encryption of the configuration data so that the encrypted configuration data can be exposed without compromising information encoded in the configuration data.

Abstract: A key is determined from a volatile response using circuitry on the device. The volatile response depend on process variation in fabrication of the device. Error control data that depends on the first volatile response can be computed, stored externally to the device, and then used to generate the key using a volatile response using the circuit. Applications of volatile keys include authentication and rights management for content and software.

Abstract: A method of automatically generating vector sequences for an observability based coverage metric supports design validation. A design validation method for Register Transfer Level (RTL) circuits includes the generation of a tag list. Each tag in the tag list models an error at a location in HDL code at which a variable is assigned a value. Interacting linear and Boolean constraints are generated for the tag, and the set of constraints is solved using an HSAT solver to provide a vector that covers the tag. For each generated vector, tag simulation is performed to determine which others of the tags in the tag list are also covered by that vector. Vectors are generated until all tags have been covered, if possible within predetermined time constraints, thus automatically providing a set of vectors which will propagate errors in the HDL code to an observable output. Performance of the design validation method is enhanced through various heuristics involving path selection and tag magnitude maximization.

Abstract: A method and apparatus for selecting a queue for service across a shared link. The method includes determining a priority for each queue (202) within a plurality of ingresses (102), wherein the priority is instantaneous for a given timeslot for data transfer, selecting a queue having a first priority for each group of queues within each ingress (104) having packets destined for a particular egress (104), selecting a queue having a second priority for each subset of queues having first priorities and having packets destined for the particular egress (104), and selecting the queue having the second priority for service across the shared link in the given timeslot.

Abstract: A method for selecting a queue for service across a shared link. The method includes classifying each queue from a group of queues within a plurality of ingresses into one tier of a number “N” of tiers. The number “N” is greater than or equal to 2. Information about allocated bandwidth is used to classify at least some of the queues into the tiers. Each tier is assigned a different priority. The method also includes matching queues to available egresses by matching queues classified within tiers with higher priorities before matching queues classified within tiers with lower priorities.

Abstract: A group of devices are fabricated based on a common design, each device having a corresponding plurality of measurable characteristics that is unique in the group to that device, each device having a measurement module for measuring the measurable characteristics. Authentication of one of the group of devices is enabled by selective measurement of one or more of the plurality of measurable characteristics of the device.