Abstract: The formation of electronic assemblies, including assemblies having an interposer, are described. In one embodiment, a method includes providing a body and forming a first metal pad layer on a first surface thereof. A second metal pad layer is formed in contact with the first patterned metal pad layer, the second metal pad layer having a denser pitch between adjacent pads than the first metal pad layer. A dielectric layer is formed between the adjacent metal pads in the first and second metal pad layers. After the forming the first and second metal pad layers and the dielectric layer, the method includes forming a plurality of vias extending through the body from a second surface thereof, the vias extending through a thickness of the body and exposing the first metal pad layer. The method also includes forming an insulating layer on sidewalls of the vias and on the second surface, and forming an electrically conductive layer on the insulating layer and on the exposed surface of the first metal layer.

Abstract: Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die.

Abstract: In one embodiment, the present invention includes a method for electroplating a plurality of metal bumps on a device side of a semiconductor wafer and planarizing the metal bumps by electropolishing to obtain a substantially uniform thickness for the plurality of metal bumps. Other embodiments are described and claimed.

Abstract: In the present invention, there is provided semiconductor devices such as a Schottky UV photodetector fabricated on n-type ZnO and MgxZn1-xO epitaxial films. The ZnO and MgxZn1-xO films are grown on R-plane sapphire substrates and the Schottky diodes are fabricated on the ZnO and MgxZn1-xO films using silver and aluminum as Schottky and ohmic contact metals, respectively. The Schottky diodes have circular patterns, where the inner circle is the Schottky contact, and the outside ring is the ohmic contact. Ag Schottky contact patterns are fabricated using standard liftoff techniques, while the Al ohmic contact patterns are formed using wet chemical etching. These detectors show low frequency photoresponsivity, high speed photoresponse, lower leakage current and low noise performance as compared to their photoconductive counterparts. This invention is also applicable to optical modulators, Metal Semiconductor Field Effect Transistors (MESFETs) and more.

Abstract: A compliant interconnect with two or more layers of metal of two or more compositions with internal stresses is described herein.

Abstract: A compliant interconnect is described that is useful for coupling semiconductor dies to other components. In one embodiment, the interconnect includes a base to couple to a first component and an arch extending from and integral with the base to couple to a second component. The interconnect may be formed by coating a substrate with photoresist, exposing the photoresist with a defined pattern, developing the photoresist, baking the photoresist at a first temperature for a first amount of time to reflow the photoresist, and baking the photoresist at a second higher temperature for a second amount of time to reflow the photoresist.

Abstract: Some embodiments of the present invention include providing high performance integrated inductors.

Abstract: Some embodiments of the present invention include integrated inductors and compliant interconnects for semiconductor packaging.

Abstract: Some embodiments of the present invention include providing high performance integrated inductors.

Abstract: Some embodiments of the present invention include integrated inductors and compliant interconnects for semiconductor packaging.

Abstract: In the present invention, there are provided self-assembled ZnO nanotips grown on relatively low temperatures on various substrates by metalorganic chemical vapor deposition (MOCVD). The ZnO nanotips are made at relatively low temperatures, giving ZnO a unique advantage over other wide bandgap semiconductors such as GaN and SiC. The nanotips have controlled uniform size, distribution and orientation. These ZnO nanotips are of single crystal quality, show n-type conductivity and have good optical properties. Selective growth of ZnO nanotips also has been realized on patterned (100) silicon on r-sapphire (SOS), and amorphous SiO2 on r-sapphire substrates. Self-assembled ZnO nanotips can also be selectively grown on patterned layers or islands made of a semiconductor, an insulator or a metal deposited on R-plane (01 12) Al2O3 substrates as long as the ZnO grows in a columnar structure along the c-axis [0001] of ZnO on these materials.

Abstract: A method for forming a composite metal layer on a substrate comprises providing nanocrystalline particles of a first metal, adding the nanocrystalline particles to a plating bath that contains ions of a second metal to form a colloid-like suspension, immersing the substrate in the plating bath, and causing a co-deposition of the second metal and the nanocrystalline particles of the first metal on the substrate to form the composite metal layer. The co-deposition may be caused by inducing a negative bias on the substrate and applying an electric current to the plating bath to induce an electroplating process. In the electroplating process, the ions of the second metal are reduced by the substrate and become co-deposited on the substrate with the nanocrystalline particles of the first metal to form the composite metal layer.

Abstract: An embodiment of a process is disclosed comprising depositing a sealing layer on a first photoresist layer formed on a substrate, the first photoresist layer having a form patterned and etched therein, depositing a second photoresist layer on the sealing layer, and curing the second photoresist layer by changing its temperature from a first temperature to a second temperature over a set period of time. An embodiment of an apparatus is disclosed comprising a substrate having a first photoresist layer thereon, the first photoresist layer having a form patterned and etched therein, a sealing layer deposited on the first photoresist layer, and a second photoresist layer on the sealing layer, wherein the second photoresist layer is cured by changing its temperature from a first temperature to a second temperature over a set period of time. Other embodiments are disclosed and claimed.

Abstract: Some embodiments of the present invention include providing high performance integrated inductors.

Abstract: An apparatus, method, and system for integrated circuit packaging having an offset solder bump are disclosed herein. A semiconductor substrate has a bond pad and a passivation layer located on an active surface thereof. A solder terminal contacts both the bond pad and passivation layer. A solder bump contacts the solder terminal and is positioned laterally offset from the bond pad.

Abstract: Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die.

Abstract: Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die.

Abstract: A compliant interconnect is described that is useful for coupling semiconductor dies to other components. In one embodiment, the interconnect includes a base to couple to a first component and an arch extending from and integral with the base to couple to a second component. The interconnect may be formed by coating a substrate with photoresist, exposing the photoresist with a defined pattern, developing the photoresist, baking the photoresist at a first temperature for a first amount of time to reflow the photoresist, and baking the photoresist at a second higher temperature for a second amount of time to reflow the photoresist.

Abstract: Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die.

Abstract: Some embodiments of the present invention include integrated inductors and compliant interconnects for semiconductor packaging.