Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells, one or more control circuits in communication with the set of non-volatile memory cells, the one or more control circuits are configured to encode data with a code rate prior to storage in the set of non-volatile memory cells, the code rate selected from two or more code rates according to one or more predictive indicators received with the data, the one or more predictive indicators relating to expected conditions for storage of the data in the set of non-volatile memory cells

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to determine a first count of bits of a representation of data that are estimated to be erroneous and a second count of bits of the representation of data that have high estimated reliability and are estimated to be erroneous. The controller is further configured to modify at least one read parameter or at least one decode parameter based on the first count and the second count.

Abstract: Technology is described herein for learning parameters for a parameterized iterative message passing decoder, and to a corresponding parameterized iterative message passing decoder. Learning the parameters may adapt the decoder to statistical dependencies introduced by the specific code's graph. Taking into account the statistical dependencies may allow the code to be shorter and/or denser. Note that the statistical dependencies in the graph may be extremely complex. Machine learning may be used to learn the parameters. The parameters may be learned when decoding data stored in the memory device. Learning the parameters may adapt the decoder to properties of data stored in the memory device, physical properties of the memory device, and/or patterns in host data.

Abstract: A device includes a memory configured to store syndromes, a first data processing unit coupled to the memory, and a second data processing unit coupled to the memory. The first data processing unit is configured to process a first value corresponding to a first symbol of data to be decoded. The second data processing unit is configured to process a second value corresponding to a second symbol of the data. Syndrome aggregation circuitry is coupled to the first data processing unit and to the second data processing unit. The syndrome aggregation circuitry is configured to combine syndrome change decisions of the first data processing unit and the second data processing unit.

Abstract: A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is operable to measure a first threshold voltage (Vt) of a memory cell under a first parameter at a read temperature and measure a second Vt of the memory cell under a second parameter at the read temperature in which the first parameter is different from the second parameter. A Vt correction term for the memory cell is determined based upon the first Vt measurement and the second Vt measurement. A read Vt of the memory cell is adjusted by using the Vt correction term.

Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

Abstract: A memory system can program data in different modes, such as normal mode programming and burst mode programming. Burst mode programming programs data into the memory device faster than normal mode programming. MLC Blocks for burst mode programming are selected based on one or more criteria, such as block age, block programming speed, or the like. Further, one or more burst mode TRIM settings, which include one or more of a program voltage TRIM setting, a step-up voltage TRIM setting, skip verify level, and a program pulse width, are used to program the blocks selected for burst mode programming. In this regard, burst mode programming is performed more quickly than normal mode programming.

Abstract: A decoder includes a processor and a scheduler coupled to the processor. The processor is configured to process a set of nodes related to a representation of a codeword during a first decode iteration. The nodes are processed in a first order. The scheduler is configured to generate a schedule that indicates a second order of the set of nodes. The second order is different from the first order.

Abstract: A device includes a non-volatile memory, a traffic analyzer, and a parameter adjuster. The traffic analyzer is configured to generate a traffic type indicator based on one or more read requests from an access device to access data at the non-volatile memory. The traffic type indicator has a first value responsive to the one or more read requests corresponding to a first traffic type and has a second value responsive to the one or more read requests corresponding to a second traffic type. The parameter adjuster is configured to designate one or more decode parameter values based on the traffic type indicator.

Abstract: In an illustrative example, a device includes a memory and a controller that is coupled to the memory and that is configured to communicate with the memory using at least a first channel and a second channel. The controller includes a bit error rate (BER) estimator configured to estimate a first BER corresponding to the first channel and a second BER corresponding to the second channel. The controller also includes a throughput balancer configured to determine whether to adjust at least one of a first clock rate of the first channel or a second clock rate of the second channel based on the first BER and the second BER.

Abstract: In an illustrative example, a device includes a memory and a controller that is coupled to the memory and that is configured to communicate with the memory using at least a first channel and a second channel. The controller includes a bit error rate (BER) estimator configured to estimate a first BER corresponding to the first channel and a second BER corresponding to the second channel. The controller also includes a throughput balancer configured to determine whether to adjust at least one of a first clock rate of the first channel or a second clock rate of the second channel based on the first BER and the second BER.

Abstract: A method of operation of a data storage device includes inputting data to a decoder of the data storage device. The method further includes sending a command to a memory of the data storage device in response to an indication of a pipeline delay associated with a decoding process to decode the data. The command indicates an operation to be performed at the memory to in response to the pipeline delay.

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to determine a first count of bits of a representation of data that are estimated to be erroneous and a second count of bits of the representation of data that have high estimated reliability and are estimated to be erroneous. The controller is further configured to modify at least one read parameter or at least one decode parameter based on the first count and the second count.

Abstract: A device includes a memory and a controller. The controller is configured to read codewords of a data structure from the memory. The codewords include a number of undecodable codewords that are undecodable at an error correction coding (ECC) decoder according to a first correction scheme. The controller includes a stripe generator and a stripe decoder. The stripe generator is configured, in response to the number of undecodable codewords exceeding an erasure correction capacity of a stripe correction scheme, to generate trial data for a stripe of the data structure, the trial data including at least one element that corresponds to erased data and at least another element that is associated with an undecodable codeword and that corresponds to valid data of the stripe. The stripe decoder is configured to initiate a stripe decode operation of the trial data.

Abstract: A device includes a memory and a controller. The controller is configured to read codewords of a data structure from the memory. The codewords include a number of undecodable codewords that are undecodable at an error correction coding (ECC) decoder according to a first correction scheme. The data structure further includes stripe parity corresponding to portions of the codewords encoded according to a stripe correction scheme. The controller is configured, in response to the number of the undecodable codewords exceeding an erasure correction capacity of the stripe correction scheme, to provide information from a stripe decoding operation to an input of a ECC decoding operation corresponding to an undecodable codeword.

Abstract: A device includes a memory device and a controller. The controller is configured to determine, based on data read from the memory device, a first count of bits of the data that are associated with at least a first number of unsatisfied parity checks of the data and a second count of bits of the data that are associated with at least a second number of unsatisfied parity checks of the data. The controller is further configured to perform one or more operations based at least partially on the first count and the second count.