Abstract: A device includes a memory configured to store syndromes, a first data processing unit coupled to the memory, and a second data processing unit coupled to the memory. The first data processing unit is configured to process a first value corresponding to a first symbol of data to be decoded. The second data processing unit is configured to process a second value corresponding to a second symbol of the data. Syndrome aggregation circuitry is coupled to the first data processing unit and to the second data processing unit. The syndrome aggregation circuitry is configured to combine syndrome change decisions of the first data processing unit and the second data processing unit.

Abstract: Apparatus and method for performing burst mode programming in a memory system are disclosed. A memory system may program data in different modes, such as normal mode programming and burst mode programming. Burst mode programming programs data into the memory device faster than normal mode programming. MLC Blocks for burst mode programming may be selected based on one or more criteria, such as block age, block programming speed, or the like. Further, one or more burst mode TRIM settings, which may include a program voltage TRIM setting, a step-up voltage TRIM setting, skip verify level, and a program pulse width, may be used to program the blocks selected for burst mode programming. In this regard, burst mode programming may be performed more quickly than normal mode programming.

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to determine a temperature-based value of a search parameter in response to detecting that an error rate of a codeword read from the memory exceeds a threshold error rate. The controller is further configured to iteratively modify one or more memory access parameters associated with reducing temperature-dependent threshold voltage variation and to re-read the codeword using the modified one or more memory access parameters.

Abstract: In an illustrative example, an apparatus includes a controller and a memory that is configured to store a codeword of a convolutional low-density parity-check (CLDPC) code. The codeword has a first size and includes multiple portions that are independently decodable and that have a second size. The controller includes a CLDPC encoder configured to encode the codeword and a CLDPC decoder configured to decode the codeword or a portion of the codeword.

Abstract: In an illustrative example, a method includes receiving data to be processed in accordance with a convolutional low-density parity-check (CLDPC) code. The method also includes processing the data based on a parity check matrix associated with the CLDPC code. The parity check matrix includes a first portion and a second portion. The first portion includes a plurality of copies of a first sub-matrix that is associated with a first sub-code, and the second portion includes a copy of second sub-matrix that is associated with a second sub-code.

Abstract: A device includes a memory and a controller. The controller is configured to read codewords of a data structure from the memory. The codewords include a number of undecodable codewords that are undecodable at an error correction coding (ECC) decoder according to a first correction scheme. The data structure further includes stripe parity corresponding to portions of the codewords encoded according to a stripe correction scheme. The controller is configured, in response to the number of the undecodable codewords exceeding an erasure correction capacity of the stripe correction scheme, to provide information from a stripe decoding operation to an input of a ECC decoding operation corresponding to an undecodable codeword.

Abstract: A device includes a memory and a controller. The controller is configured to read codewords of a data structure from the memory. The codewords include a number of undecodable codewords that are undecodable at an error correction coding (ECC) decoder according to a first correction scheme. The controller includes a stripe generator and a stripe decoder. The stripe generator is configured, in response to the number of undecodable codewords exceeding an erasure correction capacity of a stripe correction scheme, to generate trial data for a stripe of the data structure, the trial data including at least one element that corresponds to erased data and at least another element that is associated with an undecodable codeword and that corresponds to valid data of the stripe. The stripe decoder is configured to initiate a stripe decode operation of the trial data.

Abstract: A decoder includes a processor and a scheduler coupled to the processor. The processor is configured to process a set of nodes related to a representation of a codeword during a first decode iteration. The nodes are processed in a first order. The scheduler is configured to generate a schedule that indicates a second order of the set of nodes. The second order is different from the first order.

Abstract: Systems and methods of processing shaped data to include selectively performing a modification operation. The modification operation may be performed in response to determining that shaped data satisfies one or more shaping adjustment criteria. Shaping of data may be discontinued to at least a portion of a memory based on a health metric for the portion satisfying a threshold.

Abstract: A data storage device includes a memory die and a controller coupled to the memory die. The memory die includes a resistive memory and read/write circuitry configured to determine a first hard bit value and a second hard bit value of a storage element of the resistive memory. The first hard bit value and the second hard bit value are determined using opposite polarity read voltages. The controller is configured to perform error correction with respect to data read from the resistive memory.

Abstract: A data storage device includes a memory die and a controller coupled to the memory die. The memory die includes a resistive memory and read/write circuitry configured to determine a first hard bit value and a second hard bit value of a storage element of the resistive memory. The first hard bit value and the second hard bit value are determined using opposite polarity read voltages. The controller is configured to perform error correction with respect to data read from the resistive memory.

Abstract: A data storage device includes a memory die. The memory die includes a resistive memory. A method includes determining a power characteristic associated with performing a write process to write data to the resistive memory. The method further includes initiating a modified write process in response to detecting that the power characteristic satisfies a threshold.

Abstract: Systems and methods of processing shaped data to include selectively performing a modification operation. The modification operation may be performed in response to determining that shaped data satisfies one or more shaping adjustment criteria. Shaping of data may be discontinued to at least a portion of a memory based on a health metric for the portion satisfying a threshold.