Abstract: In a video decoding system, a method and system for decoding previously encoded frames of video into a compressed and uncompressed format. The uncompressed format frames may be further stored and utilized to decode additional frames of video. The compressed format frames may be further stored and provided to a display processor to be rendered with additional textures.

Abstract: Systems and methods are provided for managing performance of a computing device having dissimilar memory types. An exemplary embodiment comprises a method for interleaving dissimilar memory devices. The method involves determining an interleave bandwidth ratio comprising a ratio of bandwidths for two or more dissimilar memory devices. The dissimilar memory devices are interleaved according to the interleave bandwidth ratio. Memory address requests are distributed from one or more processing units to the dissimilar memory devices according to the interleave bandwidth ratio.

Abstract: This disclosure describes efficient transformation techniques that can be used in video coding. In particular, intermediate results of computations associated with transformation of a first block of video data are reused in the transformation of a second block of video data. The techniques may be used during a motion estimation process in which video blocks of a search space are transformed, but this disclosure is not necessarily limited in this respect. Pipelining techniques may be used to accelerate the efficient transformation techniques, and transposition memories can be implemented to facilitate efficient pipelining.

Abstract: The disclosure relates to a programmable streaming processor that is capable of executing mixed-precision (e.g., full-precision, half-precision) instructions using different execution units. The various execution units are each capable of using graphics data to execute instructions at a particular precision level. An exemplary programmable shader processor includes a controller and multiple execution units. The controller is configured to receive an instruction for execution and to receive an indication of a data precision for execution of the instruction. The controller is also configured to receive a separate conversion instruction that, when executed, converts graphics data associated with the instruction to the indicated data precision. When operable, the controller selects one of the execution units based on the indicated data precision.

Abstract: Electronic devices incorporating a heat dissipation feature include an enclosure, and at least one heat-generating component positioned within the enclosure. The heat dissipation feature is sufficiently coupled to the at least one heat-generating component to facilitate conductive heat transfer from the heat-generating component. The heat dissipation feature includes a plurality of protrusions exposed externally to the enclosure. A thermally insulating material may be disposed on at least a tip portion of at least some of the protrusions. The thermally insulating material is selected to provide a touch temperature that is below a predetermined threshold. In some instances, the thermally insulating material can provide such a touch temperature by selecting the material to include properties for thermal conductivity (k), density (?), and specific heat (Cp) such that the product of k*?*Cp results in a value less than a product of k*?*Cp for human skin.

Abstract: Efficient memory fetching techniques are described that can improve data fetching during a motion compensation decoding process. The techniques propose several different memory fetching modes that may be very efficient in different scenarios of the motion compensation decoding process. A motion compensator may a particular memory fetch mode from a plurality of possible modes on a case-by-case basis for the memory fetches associated with a motion compensation decoding process of a macroblock. The techniques described herein may be particularly useful when fractional interpolation to sub-integer pixels is used in the inter-frame compression.

Abstract: Disclosed herein is power controller for use with a graphics processing unit. The power controller monitors, manages and controls power supplied to components of a pipeline of the graphics processing unit. The power controller determining whether and to what extent power is to be supplied to a pipeline component based on status information received by the power controller in connection with the pipeline component. The power controller is capable of identifying a trend using the received status information, and determining whether and to what extent power is to be supplied to a pipeline component based on the identified trend.

Abstract: This disclosure describes an organizational scheme for memory that is useful for image processing. A memory controller architecture is also described, which takes advantage of the organizational scheme. The organizational scheme and controller architecture is particularly useful for high performance, high quality image processing of images that form a video sequence, but may also be applied in other image processing settings. The described techniques and organizational structure of the memory also allows the memory to be shared for other storage applications of a video device.

Abstract: In a video decoding system, a method and system for decoding previously encoded frames of video into a compressed and uncompressed format. The uncompressed format frames may be further stored and utilized to decode additional frames of video. The compressed format frames may be further stored and provided to a display processor to be rendered with additional textures.

Abstract: In one embodiment, this disclosure provides an encoding device comprising a mode selection engine that performs mode selection for intra-prediction encoding regardless of whether the encoding device is programmed to comply with first encoding standard or a second encoding standard. The device also includes a first encoder to perform the intra-prediction encoding according to the selected mode in compliance with the first encoding standard when the encoding device is programmed to comply with the first encoding standard, and a second encoder to perform the intra-prediction encoding according to the selected mode in compliance with the second encoding standard when the encoding device is programmed to comply with the second encoding standard. The techniques can simplify mode selection in support of multiple different intra-prediction encoding standards.

Abstract: This disclosure describes techniques that make use of a waveform fetch unit that operates to retrieve waveform samples on behalf of each of a plurality of hardware processing elements that operate simultaneously to service various audio synthesis parameters generated from one or more audio files, such as musical instrument digital interface (MIDI) files. In one example, a method comprises receiving a request for a waveform sample from an audio processing element, and servicing the request by calculating a waveform sample number for the requested waveform sample based on a phase increment contained in the request and an audio synthesis parameter control word associated with the requested waveform sample, retrieving the waveform sample from a local cache using the waveform sample number, and sending the retrieved waveform sample to the requesting audio processing element.

Abstract: This disclosure describes residual coding techniques that use vector quantization coding, which relies on template matching. However, rather than transmit vector quantization codebook indexes (or codewords) that may have no meaning to standard compliant CODECs, the techniques described herein map the residual templates to pre-computed compressed residual blocks that are compliant with a video standard. The standard compliant compressed residual blocks can then be transmitted to another device, which complies with the standard. The techniques can exploit the advantages associated with vector quantization coding, such as the ability to perform more parallel processing, while still maintaining compliance with a video coding standard.

Abstract: A system and method for intelligent decoded picture buffering is described. In one embodiment, a video bitstream buffer receives and temporarily holds an encoded compressed bitstream containing portions of a video. Then, a look ahead parser scans ahead in the video to analyze portions of the encoded video bitstream in the video bitstream buffer to predict the value of the video. Based on this prediction, an intelligent memory manager prioritizes the video portions, and then sends the high valued video portions to a first buffer and sends the low valued video portions to a second buffer.

Abstract: This disclosure describes techniques for generating a set of data points that form a triangular wave having a desired gain and a desired frequency. In one example, the method includes the step of (a) determining an increment value based on the desired frequency and the desired gain of the triangular wave. The method further includes the step of (b) adding the increment value to a current data point to generate a next data point, the current data point and the next data point forming a subset of the set of data points. The method further includes the step of iteratively performing (a) and (b) to generate the set of data points that form the triangular wave.

Abstract: This disclosure describes techniques for processing audio files that comply with the musical instrument digital interface (MIDI) format. In particular, various tasks associated with MIDI file processing are delegated between software operating on a general purpose processor, firmware associated with a digital signal processor (DSP), and dedicated hardware that is specifically designed for MIDI file processing. Alternatively, a multi-threaded DSP may be used instead of a general purpose processor and the DSP. In one aspect, this disclosure provides a method comprising parsing MIDI files and scheduling MIDI events associated with the MIDI files using a first process, processing the MIDI events using a second process to generate MIDI synthesis parameters, and generating audio samples using a hardware unit based on the synthesis parameters.

Abstract: This disclosure describes techniques that make use of a plurality of hardware elements that operate simultaneously to service synthesis parameters generated from one or more audio files, such as musical instrument digital interface (MIDI) files. In one example, a method comprises storing audio synthesis parameters generated for one or more audio files of an audio frame, processing a first audio synthesis parameter using a first audio processing element of a hardware unit to generate first audio information, processing a second audio synthesis parameter using a second audio processing element of the hardware unit to generate second audio information, and generating audio samples for the audio frame based at least in part on a combination of the first and second audio information.

Abstract: The disclosure relates to systems, methods and apparatus to convert speech to text and vice versa. One apparatus comprises a vocoder, a speech to text conversion engine, a text to speech conversion engine, and a user interface. The vocoder is operable to convert speech signals into packets and convert packets into speech signals. The speech to text conversion engine is operable to convert speech to text. The text to speech conversion engine is operable to convert text to speech. The user interface is operable to receive a user selection of a mode from among a plurality of modes, wherein a first mode enables the speech to text conversion engine, a second mode enables the text to speech conversion engine, and a third mode enables the speech to text conversion engine and the text to speech conversion engine.

Abstract: The disclosure relates to a programmable streaming processor that is capable of executing mixed-precision (e.g., full-precision, half-precision) instructions using different execution units. The various execution units are each capable of using graphics data to execute instructions at a particular precision level. An exemplary programmable shader processor includes a controller and multiple execution units. The controller is configured to receive an instruction for execution and to receive an indication of a data precision for execution of the instruction. The controller is also configured to receive a separate conversion instruction that, when executed, converts graphics data associated with the instruction to the indicated data precision. When operable, the controller selects one of the execution units based on the indicated data precision.

Abstract: This disclosure describes rate control techniques that can improve video encoding. In particular, the described rate control techniques exploit relationships between the number of bits encoded per frame and the number of non-zero coefficients of the video blocks after quantization. The number of number of non-zero coefficients of the video blocks after quantization is referred to as rho (?). The value of ? is generally proportional to the number of bits used in the video encoding. This disclosure utilizes a relationship between ? and a quantization parameter (QP) in order to achieve rate controlled video encoding. More specifically, this disclosure provides techniques for generating a lookup table (LUT) that maps values of ? to different QPs.

Abstract: The disclosure describes image processing techniques useful for devices that support image processing of different sized images. The techniques can be used in many contexts, and may be particularly useful for front-end image processing of small viewfinder images and large still images captured by the device. In one embodiment, this disclosure provides a method comprising capturing a first image with a device, processing the first image using line buffers sized to accommodate an image width of the first image, and capturing a second image with the device, wherein the second image has an image width larger than the image width first image. The method also includes processing the vertical stripes of the second image using the line buffers, wherein the vertical stripes of the second image define widths that fit into the line buffers.