Abstract: An apparatus may include a first plurality of registers, each register in the first plurality of registers configured to store data wordss, a first selector coupled to the first plurality of registers, the first selector configured to receive a data words stored in each register in the first plurality of registers, and configured to output the data words from a selected register from the first plurality of registers in response to a selection signal, a second plurality of registers, each register in the second plurality of registers configured to store a pointer associated with each register in the first plurality of registers, a second selector coupled to the second plurality of registers, the selector circuit configured to receive data from each register in the second plurality of registers, and configured to output data from a selected register from the second plurality of registers in response to the selection signal, the data comprising a pointer associated with the selected register from the first plura

Abstract: Error detection is added to a motion-picture-experts group (MPEG) decoder by checking each 8×8-pixel block for constraints. The constraints are added during compression by adjusting discrete cosine transform (DCT) coefficients in the block to meet a constraint. When the decoder determines that the constraint is not met by the DCT coefficients, an error is signaled for that block. The error can then be concealed using pixels from another frame or block. In one embodiment, the constraint is that the last two non-zero coefficients have the same magnitude. The constraint is added during compression after quantization but before variable-length coding by averaging the magnitudes and using the average magnitude for the last two non-zero coefficients. This minimizes visible distortion caused by the constraints and reduces computations.

Abstract: A decoder for motion-picture-experts group (MPEG-4) video detects start codes at the beginning of video object planes (VOP) and resync markers at the start of each video packet (VP) in the VOP. When an error occurs in the bitstream, a parser searched for a next start code or resync marker to find the start of the next video packet. A partial match of the unique start-code bit sequence signals a fuzzy match, allowing the VOP header and data to be decoded even when bit errors occur in the VOP start code. A fuzzy match of the shorter resync marker can also be enabled. Fuzzy matching of VOP start codes and resync markers allows for faster recovery from corrupted bitstreams such as those transmitted over wireless networks.

Abstract: An apparatus may include a first plurality of registers, each register in the first plurality of registers configured to store data wordss, a first selector coupled to the first plurality of registers, the first selector configured to receive a data words stored in each register in the first plurality of registers, and configured to output the data words from a selected register from the first plurality of registers in response to a selection signal, a second plurality of registers, each register in the second plurality of registers configured to store a pointer associated with each register in the first plurality of registers, a second selector coupled to the second plurality of registers, the selector circuit configured to receive data from each register in the second plurality of registers, and configured to output data from a selected register from the second plurality of registers in response to the selection signal, the data comprising a pointer associated with the selected register from the first plura

Abstract: A video encoder/decoder includes a vector pipeline unit and is configured only once by a processor to encode/decode data in accordance with any one of the JPEG, MPEG1, MPEG2 or MPEG4, H.261 or H.263 compression standards. The configuration data is stored in a configuration register of the video encoder/decoder. An optional ROM stores the configuration data for subsequent reading and loading—by the processor—into the configuration register. The vector pipeline unit includes: a run-length decoder, a binary arithmetic logic unit, a binary multiplier/divider, an accumulator, a barrel shifter, a round/modify unit, a saturate logic unit, a status register and a run-length encoder. Each component of the vector pipeline unit is optionally enabled or disabled. By disabling one or more components of the vector pipeline unit the power consumed by the encoder/decoder is reduced.