Patents by Inventor Stephen E. Luce
Stephen E. Luce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7541679Abstract: Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings such that it enters the exposed-pores, while first reactant molecules are simultaneously being outgassed. The second reactant reacts in-situ with the outgassed first reactant molecules at a mouth region of the exposed pores to form the pore-closing layer across the mouth region of exposed pores, while retaining a portion of each pore's porosity to maintain characteristics and properties of the porous low-k dielectric layer. Optionally, the first reactant may be adsorbed onto the low-k dielectric such that upon introduction of the second reactant Into the patterned dielectric openings, a reactive liner is also formed on the low-k dielectric.Type: GrantFiled: October 11, 2005Date of Patent: June 2, 2009Assignee: International Business Machines CorporationInventors: Edward C Cooney, III, John A Fitzsimmons, Jeffrey P Gambino, Stephen E Luce, Thomas L McDevitt, Lee M Nicholson, Anthony K Stamper
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Publication number: 20090124047Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.Type: ApplicationFiled: January 14, 2009Publication date: May 14, 2009Inventors: James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Robert K. Leidy, Stephen E. Luce, Richard J. Rassel, Edmund J. Sprogis
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Patent number: 7521798Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.Type: GrantFiled: November 20, 2007Date of Patent: April 21, 2009Assignee: International Business Machines CorporationInventors: James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Robert K. Leidy, Stephen E. Luce, Richard J. Rassel, Edmund J. Sprogis
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Patent number: 7521336Abstract: A crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.Type: GrantFiled: October 31, 2007Date of Patent: April 21, 2009Assignee: International Business Machines CorporationInventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Stephen E. Luce, Thomas L. McDevitt, William T. Motsiff, Mark J. Pouliot, Jennifer C. Robbins
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Publication number: 20090085152Abstract: Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.Type: ApplicationFiled: October 1, 2007Publication date: April 2, 2009Inventors: Kerry Bernstein, Timothy J. Dalton, Jeffrey P. Gambino, Mark D. Jaffe, Stephen E. Luce, Anthony K. Stamper
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Publication number: 20080116537Abstract: A CMOS image sensor array and method of fabrication. The CMOS imager sensor array comprises a substrate; an array of light receiving pixel structures formed above the substrate, the array having formed therein “m” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer; a dense logic wiring region formed adjacent to the array of light receiving pixel structures having “n” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer, where n>m. A microlens array having microlenses and color filters formed above the interlevel dielectric material layer, a microlens and respective color filter in alignment with a respective light receiving structure formed at a surface of the substrate. A top surface of the interlevel dielectric material layer beneath the microlens array is recessed from a top surface of the interlevel dielectric material layers of the dense logic wiring region.Type: ApplicationFiled: November 17, 2006Publication date: May 22, 2008Inventors: James W. Adkisson, Jeffrey P. Gambino, Zhong-Xiang He, Mark D. Jaffe, Robert K. Leidy, Stephen E. Luce, Richard J. Rassel, Edmund J. Sprogis
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Patent number: 7361989Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.Type: GrantFiled: September 26, 2006Date of Patent: April 22, 2008Assignee: International Business Machines CorporationInventors: James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Robert K. Leidy, Stephen E. Luce, Richard J. Rassel, Edmund J. Sprogis
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Publication number: 20080088014Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.Type: ApplicationFiled: September 26, 2006Publication date: April 17, 2008Inventors: James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Robert K. Leidy, Stephen E. Luce, Richard J. Rassel, Edmund J. Sprogis
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Patent number: 7335577Abstract: A crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.Type: GrantFiled: December 22, 2005Date of Patent: February 26, 2008Assignee: International Business Machines CorporationInventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Stephen E. Luce, Thomas L. McDevitt, William T. Motsiff, Mark J. Pouliot, Jennifer C. Robbins
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Patent number: 7183656Abstract: A method for connecting a microelectronic device to a wirebond comprises providing a substrate having a microelectronic circuit therein and forming a wiring layer over the substrate. The wiring layer includes a bilayer wiring structure comprising upper and lower electrically conductive layers separated by a protective electrically conductive layer. The lower layer of the bilayer structure is at the level of the wiring layer and the upper layer of the bilayer structure extends above the level of the wiring layer. The bilayer wiring structure is formed by depositing the upper and lower electrically conductive layers separated by a protective electrically conductive layer over the substrate, etching the upper electrically conductive layer and a portion of the protective electrically conductive layer, and thereafter separately etching the lower electrically conductive layer to form the wiring layer over the substrate. The method also includes connecting a wirebond to the upper layer of the bilayer structure.Type: GrantFiled: January 25, 2005Date of Patent: February 27, 2007Assignee: International Business Machines CorporationInventors: Stephen E. Luce, Thomas L. McDevitt, Anthony K. Stamper
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Patent number: 7087997Abstract: Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten as a barrier against the corrosive effects of tungsten fluoride on copper. The reduced size of the tungsten studs relative to known interface structures allows wiring and connection pads to be formed in a single aluminum layer, improving performance and reducing process time and cost.Type: GrantFiled: March 12, 2001Date of Patent: August 8, 2006Assignee: International Business Machines CorporationInventors: Lloyd G. Burrell, Edward E. Cooney, III, Jeffrey P. Gambino, John E. Heidenreich, III, Hyun Koo Lee, Mark D. Levy, Baozhen Li, Stephen E. Luce, Thomas L. McDevitt, Anthony K. Stamper, Kwong Hon Wong, Sally J. Yankee
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Patent number: 7037824Abstract: Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten as a barrier against the corrosive effects of tungsten fluoride on copper. The reduced size of the tungsten studs relative to known interface structures allows wiring and connection pads to be formed in a single aluminum layer, improving performance and reducing process time and cost.Type: GrantFiled: May 13, 2004Date of Patent: May 2, 2006Assignee: International Business Machines CorporationInventors: Lloyd G. Burrell, Edward E. Cooney, III, Jeffrey P. Gambino, John E. Heidenreich, III, Hyun Koo Lee, Mark D. Levy, Baozhen Li, Stephen E. Luce, Thomas L. McDevitt, Anthony K. Stamper, Kwong Hon Wong, Sally J. Yankee
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Patent number: 7015150Abstract: Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings such that it enters the exposed pores, while first reactant molecules are simultaneously being outgassed. The second reactant reacts in-situ with the outgassed first reactant molecules at a mouth region of the exposed pores to form the pore-closing layer across the mouth region of exposed pores, while retaining a portion of each pore's porosity to maintain characteristics and properties of the porous low-k dielectric layer. Optionally, the first reactant may be adsorbed onto the low-k dielectric such that upon introduction of the second reactant into the patterned dielectric openings, a reactive liner is also formed on the low-k dielectric.Type: GrantFiled: May 26, 2004Date of Patent: March 21, 2006Assignee: International Business Machines CorporationInventors: Edward C. Cooney, III, John A. Fitzsimmons, Jeffrey P. Gambino, Stephen E. Luce, Thomas L. McDevitt, Lee M. Nicholson, Anthony K. Stamper
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Publication number: 20040207092Abstract: Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten as a barrier against the corrosive effects of tungsten fluoride on copper. The reduced size of the tungsten studs relative to known interface structures allows wiring and connection pads to be formed in a single aluminum layer, improving performance and reducing process time and cost.Type: ApplicationFiled: May 13, 2004Publication date: October 21, 2004Inventors: Lloyd G. Burrell, Edward E. Cooney, Jeffrey P. Gambino, John E. Heidenreich, Hyun Koo Lee, Mark D. Levy, Baozhen Li, Stephen E. Luce, Thomas L. McDevitt, Anthony K. Stamper, Kwong Hon Wong, Sally J. Yankee
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Patent number: 6762108Abstract: The present invention provides a method of forming a capacitor in a last metal wiring layer, and the structure so formed. The invention further provides a spacer formed around the capacitor to electrically isolate portions of the capacitor.Type: GrantFiled: September 27, 2002Date of Patent: July 13, 2004Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Stephen E. Luce, Thomas L. McDevitt, Henry W. Trombley
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Publication number: 20030025139Abstract: The present invention provides a method of forming a capacitor in a last metal wiring layer, and the structure so formed. The invention further provides a spacer formed around the capacitor to electrically isolate portions of the capacitor.Type: ApplicationFiled: September 27, 2002Publication date: February 6, 2003Inventors: Jeffrey P. Gambino, Stephen E. Luce, Thomas L. McDevitt, Henry W. Trombley
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Patent number: 6504203Abstract: The present invention provides a method of forming a capacitor in a last metal wiring layer, and the structure so formed.Type: GrantFiled: February 16, 2001Date of Patent: January 7, 2003Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Stephen E. Luce, Thomas L. McDevitt, Henry W. Trombley
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Publication number: 20020127846Abstract: Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten as a barrier against the corrosive effects of tungsten fluoride on copper. The reduced size of the tungsten studs relative to known interface structures allows wiring and connection pads to be formed in a single aluminum layer, improving performance and reducing process time and cost.Type: ApplicationFiled: March 12, 2001Publication date: September 12, 2002Inventors: Lloyd G. Burrell, Edward E. Cooney, Jeffrey P. Gambino, John E. Heidenreich, Hyun Koo Lee, Mark D. Levy, Baozhen Li, Stephen E. Luce, Thomas L. McDevitt, Anthony K. Stamper, Kwong Hon Wong, Sally J. Yankee
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Publication number: 20020117703Abstract: The present invention provides a method of forming a capacitor in a last metal wiring layer, and the structure so formed. The invention further provides a spacer formed around the capacitor to electrically isolate portions of the capacitor.Type: ApplicationFiled: February 16, 2001Publication date: August 29, 2002Inventors: Jeffrey P. Gambino, Stephen E. Luce, Thomas L. McDevitt, Henry W. Trombley
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Patent number: 6426557Abstract: A controlled collapse chip connection (C4) structure having stronger resistance to failure is constructed for use with integrated circuit devices having copper wiring. Failure resistance is obtained by replacing the mechanically weak final passivation to copper interface. The weak interface is eliminated by use of a specific peg on peg structure together with a layer of shunt metal having excellent adhesion and barrier characteristics. A shunt metal, e.g., Ta or TaN, is placed between both the copper and final passivation and the copper and C4 metals such that it overlaps the edge of the peg defined wiring mesh to encase the copper. Overlap is obtained by the peg on peg structure where a SiO2 peg defines the copper wire mesh and a smaller Si3N4 peg placed on the SiO2 peg defines the overlap above the mesh wire and provides the ability to pattern the overlayer shunt without exposure of the copper conductor.Type: GrantFiled: February 25, 2000Date of Patent: July 30, 2002Assignee: International Business Machines CorporationInventors: Timothy Daubenspeck, Stephen E. Luce, William Motsiff