Patents by Inventor Stephen E. Luce

Stephen E. Luce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6251787
    Abstract: Eliminating exposure of PN junctions to light capable of invoking a photovoltaic effect and/or inhibiting the oxidation and reduction reactions induced by the photovoltaic effect prevents the electrochemical dissolution of metal components on semiconductor devices by electrolysis. A darkened enclosure for use on tools for wafer CMP, brush cleaning, unloading, and rinsing will eliminate exposure. Alternatively, illumination of a semiconductor wafer can be limited to wavelengths of light that do not provide enough energy to induce a photovoltaic effect. An inhibitor in the CMP slurry and/or post-CMP water rinse blocks the oxidation and/or reduction reactions. A blocking agent, such as a high molecular weight surfactant, will interfere with both the oxidation and reduction reactions at the metal surface. Also, a poisoning agent will impede the reduction portion of electrolysis.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: June 26, 2001
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Wilma J. Horkans, Stephen E. Luce, Naftall E. Lustig, Keith R. Pope, Peter D. Roper
  • Patent number: 6153043
    Abstract: Eliminating exposure of PN junctions to light capable of invoking a photovoltaic effect and/or inhibiting the oxidation and reduction reactions induced by the photovoltaic effect prevents the electrochemical dissolution of metal components on semiconductor devices by electrolysis. A darkened enclosure for use on tools for wafer CMP, brush cleaning, unloading, and rinsing will eliminate exposure. Alternatively, illumination of a semiconductor wafer can be limited to wavelengths of light that do not provide enough energy to induce a photovoltaic effect. An inhibitor in the CMP slurry and/or post-CMP water rinse blocks the oxidation and/or reduction reactions. A blocking agent, such as a high molecular weight surfactant, will interfere with both the oxidation and reduction reactions at the metal surface. Also, a poisoning agent will impede the reduction portion of electrolysis.
    Type: Grant
    Filed: February 6, 1998
    Date of Patent: November 28, 2000
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Wilma J. Horkans, Stephen E. Luce, Naftali E. Lustig, Keith R. Pope, Peter D. Roper
  • Patent number: 5985762
    Abstract: A copper diffusion barrier is formed on the side walls of vias connected to copper conductors to prevent copper diffusion into inter-level dielectric. A thin film of copper diffusion barrier material is deposited on the wafer post via etch. A sputter etch is performed to remove barrier material from the base of via and to remove copper oxide from the copper conductor. The barrier material is not removed from the sidewall during the sputter etch. Thus, a barrier to re-deposited copper is formed on the via sidewalls to prevent copper poisoning of the dielectric.
    Type: Grant
    Filed: May 19, 1997
    Date of Patent: November 16, 1999
    Assignee: International Business Machines Corporation
    Inventors: Robert M. Geffken, Stephen E. Luce
  • Patent number: 5521434
    Abstract: A fabrication method and resultant electronic module having one or more surfaces enhanced with interconnects and components. Electronic modules having, for example, resistors and capacitors integral with a side surface thereof are disclosed. Further described are electronic modules with interconnects electrically attaching for example, side to side, or side to end surfaces are described. Moreover, discussion of an electronic module having a Silicon Front Face chip is contained herein. Specific details of the fabrication method, resulting electronic module, and related wafer processing are set forth.
    Type: Grant
    Filed: October 17, 1994
    Date of Patent: May 28, 1996
    Assignee: International Business Machines Corporation
    Inventors: John E. Cronin, Stephen E. Luce, Steven H. Voldman
  • Patent number: 5486267
    Abstract: The invention provides a method for substrate preparation prior to applying photoresist to the substrate. A substrate, such as a TEOS-based silicon dioxide or silicon nitride film, is selected and treated with reactive oxygen. The reactive oxygen can comprise ozone or ozone plasma, for example. After treatment of the substrate, the photoresist, preferably an acid-catalyzed photoresist for use with deep UV sensitization, is applied.
    Type: Grant
    Filed: February 28, 1994
    Date of Patent: January 23, 1996
    Assignee: International Business Machines Corporation
    Inventors: Stephen E. Knight, Stephen E. Luce, Thomas L. McDevitt
  • Patent number: 5480748
    Abstract: A conductive layer in a semiconductor device is protected against chemical attack by a photoresist developer by forming a protective film overlying the conductive layer. The protective film is formed using a chemical reaction that occurs through defects in a passivation layer that was previously formed overlying the conductive layer. The chemical reaction substantially occurs at the surface of the conductive layer and chemically converts portions thereof in forming the protective film. Preferably, the conductive layer is aluminum or an alloy thereof containing copper and/or silicon, and the protective film is aluminum oxide formed on the aluminum layer to protect it from corrosion by tetramethyl ammonium hydroxide (TMAH). The passivation layer is TiN, and the chemical reaction used is oxidation of the aluminum layer through defects in the overlying TiN layer by placing in an ozone asher.
    Type: Grant
    Filed: April 26, 1994
    Date of Patent: January 2, 1996
    Assignee: International Business Machines Corporation
    Inventors: Paul E. Bakeman, Jr., Hyun K. Lee, Stephen E. Luce
  • Patent number: 5384281
    Abstract: A process for etching narrow features, particularly submicron borderless contacts, in a semiconductor substrate is disclosed. The process comprises depositing, by an orientation-sensitive technique, film which will act as an etch stop. The film is significantly thicker on horizontal surfaces than on vertical. A second layer is deposited and then etched using the first film as an etch stop. In one embodiment the etch stop is composed of an oxidizable material.
    Type: Grant
    Filed: December 29, 1992
    Date of Patent: January 24, 1995
    Assignee: International Business Machines Corporation
    Inventors: Donald M. Kenney, Stephen E. Luce
  • Patent number: 5219788
    Abstract: A process of patterning a conductive layer on a substrate avoiding webbing yet permitting high density patterning places two layers between the resist and the metal. The first layer is an antireflective coating such as titanium nitride applied to the metal. The second layer is a barrier comprising silicon such as sputtered silicon or SiO.sub.2. The barrier layer may also be a thin coating of spin-on glass. The barrier layer prevents interaction between the TiN and acid groups which are generated during exposure of the resist. With this structure in place the resist is applied, exposed and developed.
    Type: Grant
    Filed: February 25, 1991
    Date of Patent: June 15, 1993
    Assignee: IBM Corporation
    Inventors: John R. Abernathey, Timothy H. Daubenspeck, Stephen E. Luce, Denis J. Poley, Rosemary A. Previti-Kelly, Gary P. Viens, Jung H. Yoon
  • Patent number: 4944682
    Abstract: A method of forming semi-conductor devices components wherein there are at least two exposed conducting regions having passivating material overlying said regions. The passivating material is subject to etching by a given etchant. At least one, but less than all of the regions are covered with a material, preferably an electrical conducting material, which also preferably covers additional electrical conducting or semi-conducting regions. Thereafter, all the regions are subjected to the given etchant, but only those regions having the passivating material not covered with the etch resistant material are removed. Preferably, at this point, a layer of conducting material is deposited over all the regions.
    Type: Grant
    Filed: December 21, 1989
    Date of Patent: July 31, 1990
    Assignee: International Business Machines Corporation
    Inventors: John E. Cronin, Susan F. Cronin, Carter W. Kaanta, Charles W. Koburger, III, Stephen E. Luce, Dale J. Pearson