Abstract: A process for aligning at least two layers in an abutting relationship with each other comprises forming a plurality of sprocket openings in each of the layers for receiving a sprocket of diminishing diameters as the sprocket extends outwardly from a base, with the center axes of the sprocket openings in each layer being substantially alignable with one another, the diameter of the sprocket openings in an abutting layer for first receiving the sprocket being greater than the diameter of the sprocket openings in an abutted layer. This is followed by forming a plurality of reservoir openings in each of at least two of the layers and positioning the sprocket openings in the layers to correspond with one another and the reservoir openings in the layers to correspond with one another so that substantial alignment of the center axes of the corresponding sprocket openings in the layers effects substantial alignment of the center axes of the corresponding reservoir openings in the layers.

Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

Abstract: A process for aligning at least two layers in an abutting relationship with each other comprises forming a plurality of sprocket openings in each of the layers for receiving a sprocket of diminishing diameters as the sprocket extends outwardly from a base, with the center axes of the sprocket openings in each layer being substantially alignable with one another, the diameter of the sprocket openings in an abutting layer for first receiving the sprocket being greater than the diameter of the sprocket openings in an abutted layer. This is followed by forming a plurality of reservoir openings in each of at least two of the layers and positioning the sprocket openings in the layers to correspond with one another and the reservoir openings in the layers to correspond with one another so that substantial alignment of the center axes of the corresponding sprocket openings in the layers effects substantial alignment of the center axes of the corresponding reservoir openings in the layers.

Abstract: A semiconductor solder bump structure having a solder bump with at least a first solder and a second solder attached to the first solder, producing one solder bump having at least two different solders with different melting temperatures. A method of fabricating the solder is included.

Abstract: An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a second material having a second thermal expansivity. The second thermal expansivity is different from the first thermal expansivity so that there is a coefficient of thermal expansion mismatch between the substrate and the interposer or chip. The interposer is coupled to the substrate via a first plurality of electrical contacts and an underfill adhesive at least partially surrounding the electrical contacts to bond the interposer to the substrate and thereby reduce strain on the first plurality of electrical contacts. The integrated circuit chip is coupled to the interposer via a second plurality of electrical contacts only, without use of an adhesive surrounding the second plurality of electrical contacts.

Abstract: The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.

Abstract: A portion of compliant material includes four walls defining a slot. The slot has a relatively large cross-section end in fluid communication with a solder reservoir, and also has a relatively small cross-section end opposed to the relatively large cross-section end. The slot has a generally elongate rectangular shape when viewed in plan, with a length perpendicular to a scan direction, a width, parallel to the scan direction, associated with the relatively large cross section end, and a width, parallel to the scan direction, associated with the relatively small cross section end. The slot is configured in the portion of compliant material such that the relatively small cross-section end of the slot normally remains substantially closed, but locally opens sufficiently to dispense solder from the reservoir when under fluid pressure and locally unsupported by a workpiece. Methods of operation and fabrication are also disclosed.

Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

Abstract: A method of stacking a chip, including an integrated circuit, onto a substrate including applying an anisotropic conductive film (ACF) or a solder-filled conductive film onto a surface thereof, the surface being configured to electrically couple to the film, placing the chip onto the film, the chip being configured to electrically couple to the film, compressively pressurizing the chip, the film and the surface such that the chip is electrically coupled to the surface via the film,, testing the chip to determine whether the chip is operating normally, reworking the placement of the chip onto the film and repeating the compressive pressurization if the chip is determined to not be operating normally, repeating the testing to determine whether the chip is operating normally, and once the chip is determined to be operating normally, bonding the chip, the film and the surface.

Abstract: A semiconductor solder bump structure having a solder bump with at least a first solder and a second solder attached to the first solder, producing one solder bump having at least two different solders with different melting temperatures. A method of fabricating the solder is included.

Abstract: Improved interconnects are produced by injection molded solder which fills mold arrays with molten solder so that columns that have much greater height to width aspect ratios greater than one are formed, rather than conventional flip chip bumps. The columns may have filler particles or reinforcing conductors therein. In the interconnect structures produced, the cost and time of a subsequent underfill step is reduced or avoided. The problem of incompatibility with optical interconnects between chips because underfills require high loading of silica fillers which scatter light, is solved, thus allowing flip chips to incorporate optical interconnects.

Abstract: A method of forming coaxial solder bumps, which, in essence, provide rigid supports, with the use of hole-producing stencils being formed on a polymer insulator on a sacrificial substrate, wherein posts are formed within a ring structure. The holes are then filled with solder utilizing injection molding of solder, whereby both the ring and post are filled with solder, but are electrically insulated from each other, so as to provide inner and outer coaxial connections.

Abstract: A process for aligning at least two layers in an abutting relationship with each other comprises forming a plurality of sprocket openings in each of the layers for receiving a sprocket of diminishing diameters as the sprocket extends outwardly from a base, with the center axes of the sprocket openings in each layer being substantially alignable with one another, the diameter of the sprocket openings in an abutting layer for first receiving the sprocket being greater than the diameter of the sprocket openings in an abutted layer. This is followed by forming a plurality of reservoir openings in each of at least two of the layers and positioning the sprocket openings in the layers to correspond with one another and the reservoir openings in the layers to correspond with one another so that substantial alignment of the center axes of the corresponding sprocket openings in the layers effects substantial alignment of the center axes of the corresponding reservoir openings in the layers.

Abstract: The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.

Abstract: A wafer-scale apparatus and method is described for the automation of forming, aligning and attaching two-dimensional arrays of microoptic elements on semiconductor and other image display devices, backplanes, optoelectronic boards, and integrated optical systems. In an ordered fabrication sequence, a mold plate comprised of optically designed cavities is formed by reactive ion etching or alternative processes, optionally coated with a release material layer and filled with optically specified materials by an automated fluid-injection and defect-inspection subsystem. Optical alignment fiducials guide the disclosed transfer and attachment processes to achieve specified tolerances between the microoptic elements and corresponding optoelectronic devices and circuits.

Abstract: The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.

Abstract: A process of copper plating a through-hole in a printed circuit board, and the printed circuit board made from such process. The process comprises: providing a printed circuit board with at least two copper interconnect lines separated by an insulator in the vertical direction; providing a through-hole in the printed circuit board in the vertical direction such that the interconnect lines provide a copper land in the through-hole; applying a seed layer to an interior surface of the through-hole; removing an outermost portion of the seed layer from the interior surface of the through-hole with a laser; applying copper on the seed layer.

Abstract: A process of copper plating a through-hole in a printed circuit board, and the printed circuit board made from such process. The process comprises: providing a printed circuit board with at least two copper interconnect lines separated by an insulator in the vertical direction; providing a through-hole in the printed circuit board in the vertical direction such that the interconnect lines provide a copper land in the through-hole; applying a seed layer to an interior surface of the through-hole; removing an outermost portion of the seed layer from the interior surface of the through-hole with a laser; applying copper on the seed layer.

Abstract: A wafer-scale apparatus and method is described for the automation of forming, aligning and attaching two-dimensional arrays of microoptic elements on semiconductor and other image display devices, backplanes, optoelectronic boards, and integrated optical systems. In an ordered fabrication sequence, a mold plate comprised of optically designed cavities is formed by reactive ion etching or alternative processes, optionally coated with a release material layer and filled with optically specified materials by an automated fluid-injection and defect-inspection subsystem. Optical alignment fiducials guide the disclosed transfer and attachment processes to achieve specified tolerances between the microoptic elements and corresponding optoelectronic devices and circuits.

Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.