Abstract: A tetherless system-in-package includes a first integrated circuit (IC) chip having interconnects and energy harvesting elements. A super-capacitor is configured to store a charge output by the energy harvesting elements. At least a second IC chipset including a smart chip and an optical I/O or an RF I/O is aligned and bonded to at least one of the interconnects of the first IC chip. The first IC chip and the second IC chip are configured to receive a portion of the charge stored by the super-capacitor.

Abstract: A method of forming a photovoltaic device that includes ion implanting a first conductivity type dopant into first regions of a semiconductor layer of an SOI substrate, wherein the first regions are separated by a first pitch; and ion implanting a second conductivity type dopant into second regions of the semiconductor layer of the SOI substrate. The second regions are separated by a second pitch. Each second conductivity type implanted region of the second regions is in direct contact with first conductivity type implanted region of the first regions to provide a plurality of p-n junctions, and adjacent p-n junctions are separated by an intrinsic portion of the semiconductor layer to provide P-I-N cells that are horizontally oriented.

Abstract: An active cooling structure, comprising a non-superconducting layer, a superconducting layer, and an array of Superconductor-Insulator-Normal Metal (NIS) tunnel junctions. The non-superconducting layer may comprise a plurality of non-superconducting traces. The superconducting layer may comprise a plurality of superconducting traces. The array of Superconductor-Insulator-Normal Metal (NIS) tunnel junctions may be located between the plurality of non-superconducting traces and the plurality of superconducting traces.

Abstract: One or more trenches in a silicon substrate have an electrically active surface at a trench base and metal layer disposed on the electrically active surface. Precursor materials are disposed and/or formed on the metal layer in the trench. An anode is patterned either exclusively in the 3D trench or in the 3D trench, sidewalls and field of the substrate, where the anode patterning transforms and/or moves the precursor materials in the trench into some novel compositions of matter and other final operational structures for the device, e.g. layers of metallic Lithium for energy storage and different concentrations of Lithium-silicon species in the substrate. A multi-faceted mechanism is disclosed for Al2O3 silicon interfacial additives. When the anode is patterned both in and outside the 3D wells, Al2O3 provides an for electron-conductive Li-metal interface that enables homogenous plating on both the insulated substrate field as well as active silicon trench base where Al2O3 acts as a barrier to Li—Si diffusion.

Abstract: Techniques are disclosed for fabricating and using a neuromorphic computing device including biological neurons. For example, a method for fabricating a neuromorphic computing device includes forming a channel in a first substrate and forming at least one sensor in a second substrate. At least a portion of the channel in the first substrate is seeded with a biological neuron growth material. The second substrate is attached to the first substrate such that the at least one sensor is proximate to the biological neuron growth material and growth of the seeded biological neuron growth material is stimulated to grow a neuron in the at least a portion of the channel.

Abstract: A PCM cell is provided that includes a silver (Ag) doped Ge2Sb2Te5 (GST) alloy layer as the PCM material. The PCM cell containing the Ag doped GST alloy layer exhibits a reduced reset state resistance drift as compared to an equivalent PCM cell in which a non-Ag doped GST alloy layer is used. In some embodiments and depending on the Ag dopant concentration of the Ag doped GST alloy layer, a constant reset state resistance or even a negative reset state resistance drift can be obtained.

Abstract: A method for making a hydrophobic biosensing device includes forming alternating layers over a top and sides of a fin on a dielectric layer to form a stack of layers. The stack of layers are planarized to expose the top of the fin. The fin and every other layer are removed to form a cathode group of fins and an anode group of fins. A hydrophobic surface on the two groups of fins.

Abstract: In an embodiment, a fabrication method comprises forming first and second electrodes over a substrate that includes a nanowire that extends between, and beneath portions of, the first and second electrodes. The method also includes forming a mask structure that defines at least one opening over a portion of the nanowire and defines at least one overhang portion over a gap between the substrate and the mask. The method further includes depositing a first gate electrode on the substrate and overlapping a third region of the nanowire, and depositing a second gate electrode on the substrate and overlapping a fourth region of the nanowire. The depositing of the first gate electrode includes depositing conductive material through the at least one opening from a first oblique angle, and the depositing of the second gate electrode includes depositing conductive material through the at least one opening from a second oblique angle.

Abstract: According to an embodiment of the present invention, a method for fabricating a Majorana fermion structure includes providing a substrate, and depositing a superconducting material on the substrate. The method includes depositing a magnetic material on the superconducting material using angled deposition through a mask. The method includes annealing the magnetic material and the superconducting material to form a magnetic nanowire partially embedded in the superconducting material such that the magnetic nanowire and the superconducting material form a Majorana fermion structure.

Abstract: A semiconductor device includes a substrate and a buffer layer disposed on a first portion, a second portion, and a third portion of the substrate. The semiconductor device further includes a multilayer light-emitting diode (LED) stack disposed on the first portion of the substrate, and an optical sensor disposed on the second portion of the substrate. The semiconductor device further includes at least one electrode disposed on the third portion of the substrate, a first conductor in contact with the multilayer LED stack, and a second conductor in contact with the optical sensor. The at least one electrode, the first conductor, and the second conductor are formed of a glassy carbon material.

Abstract: An apparatus includes an analog phase change memory array, including an array of cells addressable and accessible through first lines and second lines. The apparatus includes device(s) coupled to one or more of the first lines. The device(s) is/are able to be coupled to or decoupled from the one or more first lines to compensate for phase change memory resistance drift in resistance of at least one of the cells in the one or more first lines. The apparatus may also include control circuitry configured to send, using the first lines and second lines, a same set pulse through the device(s) to multiple individual phase change memory resistors in the phase change memory array sequentially once every period.

Abstract: An energy storage device for an integrated circuit carrier package. One or more energy storage elements have contact elements arranged thereon that include an anode, a cathode, and an isolated common pad. The energy storage element is configured for arrangement in a stack of energy storage elements in which the isolated common pad is shorted to one of the anode or the cathode by bonded conductive interconnects.

Abstract: An energy storage device for an integrated circuit carrier package. One or more energy storage elements have contact elements arranged thereon that include an anode, a cathode, and an isolated common pad. The energy storage element is configured for arrangement in a stack of energy storage elements in which the isolated common pad is shorted to one of the anode or the cathode by bonded conductive interconnects.

Abstract: A tetherless system-in-package includes a first integrated circuit (IC) chip having interconnects and energy harvesting elements. A super-capacitor is configured to store a charge output by the energy harvesting elements. At least a second IC chipset including a smart chip and an optical I/O or an RF I/O is aligned and bonded to at least one of the interconnects of the first IC chip. The first IC chip and the second IC chip are configured to receive a portion of the charge stored by the super-capacitor.

Abstract: Systems and techniques that facilitate quantum tuning via permanent magnetic flux elements are provided. In various embodiments, a system can comprise a qubit device. In various aspects, the system can further comprise a permanent magnet having a first magnetic flux, wherein an operational frequency of the qubit device is based on the first magnetic flux. In various instances, the system can further comprise an electromagnet having a second magnetic flux that tunes the first magnetic flux. In various cases, the permanent magnet can comprise a nanoparticle magnet. In various embodiments, the nanoparticle magnet can comprise manganese nanoparticles embedded in a silicon matrix. In various aspects, the system can further comprise an electrode that applies an electric current to the nanoparticle magnet in a presence of the second magnetic flux, thereby changing a strength of the first magnetic flux.

Abstract: A bottom electrode is deposited on top of a substrate. A dielectric material layer is deposited on top of the bottom electrode. A hole is created in the dielectric material layer. A lift off layer is spun on and baked on the dielectric material layer. A photoresist layer is spun on and baked on the lift off layer. UV lithography is performed to create an opening above the hole in the dielectric material layer. An Ag layer is deposited on top of the remaining patterned dielectric material layer and the photoresist layer. A Germanium Antimony Telluride (GST) layer is deposited on top of the Ag layer. A top electrode is deposited on top of the GST layer. The Ag layer, the GST layer, and the top electrode located on top of the photoresist layer along with the photoresist layer and the lift off layer are removed.

Abstract: A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of a first surface of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. The sensing region and a portion of the device region of the superconductor layer are exposed. A sensing region contact is formed by coupling the first surface of the semiconductor layer with a first metal layer. A nanorod contact using the first metal within the portion of the device region outside the sensing region is formed. By depositing a second metal layer on a second surface of the semiconductor layer within the sensing region, a tunnel junction gate is formed.

Abstract: A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. Using an etching process subsequent to the implanting, the sensing region and a portion of the device region of the superconductor layer adjacent to the isolation region are exposed. By depositing a first metal layer within the sensing region, a tunnel junction gate is formed. A sensing region gate is formed by coupling the semiconductor layer with a second metal layer. A nanorod contact using the second metal within the portion of the device region outside the sensing region is formed.

Abstract: An apparatus includes an analog phase change memory array, including an array of cells addressable and accessible through first lines and second lines. The apparatus includes device(s) coupled to one or more of the first lines. The device(s) is/are able to be coupled to or decoupled from the one or more first lines to compensate for phase change memory resistance drift in resistance of at least one of the cells in the one or more first lines. The apparatus may also include control circuitry configured to send, using the first lines and second lines, a same set pulse through the device(s) to multiple individual phase change memory resistors in the phase change memory array sequentially once every period.

Abstract: According to an embodiment of the present invention, a method for fabricating a Majorana fermion structure includes providing a substrate, and depositing a superconducting material on the substrate. The method includes depositing a magnetic material on the superconducting material using angled deposition through a mask. The method includes annealing the magnetic material and the superconducting material to form a magnetic nanowire partially embedded in the superconducting material such that the magnetic nanowire and the superconducting material form a Majorana fermion structure.