Abstract: The present invention provides a passive RFID chip with on-chip charge pumps for generating electrical power for the chip from radio frequencies. The passive RFID chip comprises an analog portion and a digital portion. The analog portion primarily comprises a voltage sensor and an AM data detector. The digital portion comprises a state machine digital logic controller. Incoming RF signals enter the chip via external antennas. The RF signals are converted into regulated DC signals by RF-DC converters with the voltage sensor. The RF-DC converters provide power for all the on-chip components and hence the chip does not require external power supply. The incoming RF signals are demodulated by demodulators and enter the AM data detector where the envelope transitions are detected. A voltage alarm is provided to ensure the voltage level does not drop below an operational level of the chip.

Abstract: An AV switching method capable of auto-configuring a plurality of AV input signals and associated apparatus is provided. An audio-video detector capable of auto-configuring the AV input signals includes an audio-video detecting module, an impedance adjustment module, and an audio-video switching module. The audio-video detecting module receives and detects the AV input signals to generate an AV detecting result. The impedance adjustment module adjusts matching impedance for the AV input signals according to the AV detecting result. The audio-video switching module switches the AV input signals to output AV output signals according to the AV detecting result.

Abstract: A video scaling apparatus includes a receiver for receiving incoming video signals having transmitted therein a plurality of incoming frames, each incoming frame having a first plurality of synchronization signals for indicating lines in the incoming frame; a scaler with a line extender for generating outgoing video signals having transmitted therein a plurality of outgoing frames, each outgoing frame having a second plurality of synchronization signals for indicating lines in the outgoing frame, and for generating an outgoing frame for each incoming frame. The line extender ensures durations of all lines in the outgoing video signals are of substantially equal length. By ensuring that all lines in the outgoing frame are of substantially the same length, the reliability of a display device receiving the outgoing video signals is increased. Additionally, the frequency requirements of an outgoing clock for the video signals can be less stringent.

Abstract: The present invention provides a phase-locked loop that comprises a divider, a noise-shaped quantizer, a filter, a phase detector and digital loop filter. The divider is used for receiving a reference clock with a substantially fixed period and generating an output clock with a time-varying period. The noise-shaped quantizer is used for quantizing a period control word to a time-varying value in response to the output clock fed from the divider so that the divider generates the output clock by means of dividing the reference clock by the time-varying value. The filter is employed to substantially filter out jitter from the output clock. The phase detector is used for generating a phase error in response to the filtered output clock and an input signal. The digital loop filter is used for generating the period control word in response to the phase error.

Abstract: A flat panel display device, LCD controller and associated method is provided. The flat panel display device includes a display panel, a lamp for providing a backlight source for the display panel, a power transformation module for providing a power source for the lamp, a non-volatile storage unit for storing program code, and a display controller. The display controller includes an image processing module for processing image data and outputting processed results to the display panel, and a digital pulse width modulation module for adjusting on and off time of the power transformation module according to a synchronization signal.

Abstract: A flat panel display device, LCD controller and associated method is provided. The flat panel display device includes a display panel, a lamp for providing a backlight source for the display panel, a power transformation module for providing a power source for the lamp, a non-volatile storage unit for storing program code, and a display controller. The display controller includes an image processing module for processing image data and outputting processed results to the display panel, and a digital pulse width modulation module for adjusting on and off time of the power transformation module with reference to a synchronization signal.

Abstract: A clock generator capable of providing reduced low-frequency jitter clock signals without utilization of a crystal oscillator is introduced. The present invention clock generator utilizes a diode in related biasing circuit such that the generated control current to a current control oscillator is stable and clear due to the low flicker noise and low thermal noise of the voltage across the diode. The cost of PLL systems utilizing the present invention clock generator instead of a crystal oscillator is decreased. The adopted biasing circuit is introduced as well.

Abstract: A level clamping control circuit and associated level clamping control method are provided. The level clamping control circuit includes a reference level estimator, a subtractor, a clamping computation circuit, a dithering circuit, and a digital-to-analog converter (DAC). The reference level estimator estimates a reference level of the input signal. The subtractor computes a difference between the reference level and a desired reference level to output a difference signal. The clamping computation circuit generates a first control value according to the difference signal. The dithering circuit dithers the first control value to alternately output a plurality of second control values. Finally, the DAC respectively utilizes the second control values to charge or discharge a capacitor to adjust the reference level of the input signal.

Abstract: An analog-to-digital converting system with automatic gain control. The analog-to-digital converting system includes a programmable gain amplifier (PGA) for receiving and amplifying an input signal by a gain factor to generate an amplified input signal; an ADC, coupled to the PGA, for converting the amplified input signal into a digital signal according to an actual reference voltage signal; and an automatic gain controller, coupled to the PGA and the ADC, for jointly controlling the gain factor set to the PGA and the actual reference voltage signal set to the ADC according to a hysteretic behavior.

Abstract: An analog-to-digital converting system for converting a composite video signal into a digital signal according to a synchronized clock. The analog-to-digital converting system includes an analog-to-digital converter (ADC), a color burst phase estimator and a phase-locked loop (PLL). The ADC converts the composite video signal to the digital signal according to the synchronized clock, wherein the synchronized clock is synchronized to a frequency of a color burst of a chrominance signal of the composite video signal. The color burst phase estimator, coupled to the ADC, estimates the phase of the color burst carried on the composite video signal. The PLL, coupled to the color burst phase estimator, generates the synchronized clock according to the phase of the color burst estimated by the color burst phase estimator.

Abstract: A video signal processing system capable of adjusting errors and related methods are introduced. The video signal processing system and related calibration methods utilize the characteristic of periodic breaks of video signals to perform various kinds of calibrations including gain calibration of ADC, offset calibration of ADC, dc-level shifting of input signals, and quatization errors spreading by adding analog random signals to input video signals. The required high accuracy in video signal processing systems is achieved in the present invention with the claimed calibration methods.

Abstract: A batteryless remote control device and associated method is provided. The batteryless remote control device comprises a plurality of buttons; an RFID circuit with a nonvolatile memory, coupled to the buttons; and an antenna, coupled to the RFID circuit, for transceiving an RF signal. The remote control method for a digital home appliance to be remote controlled by a batteryless remote control device comprising the following steps. The digital home appliance determines if a first RFID is present. Then, an electromagnetic wave is broadcasted. The digital home appliance receives a control packet from the batteryless remote control device and operates according to the control packet and a hierarchy information.

Abstract: An apparatus and method for masking interference noise contained in a signal source. According to the present invention, the apparatus comprises: a pseudo random binary sequence generator for generating a digital dither signal; a scrambler for receiving an offset signal and generating a dithered offset signal by scrambling the offset signal with the digital dither signal; a digital-to-analog converter for converting the dithered offset signal into an analog dithered offset signal; a summing device for generating a dithered image signal in response to the analog dithered offset signal and the analog image signal; and an analog-to-digital converter for converting the dithered image signal into the digital image signal.

Abstract: A logic system with adaptive supply voltage control comprising a logic circuit clocked by a clock signal from a clock generating circuit and a voltage conversion circuit for generating a dynamically regulated supply voltage for powering the logic circuit. A critical path delay of the logic circuit is designed to be equal to or shorter than a period of the clock signal. The voltage conversion circuit dynamically regulates the supply voltage of the logic circuit based on a bias voltage of the clock generating circuit. According to the invention, the power consumption is effectively minimized while ensuring the logic circuit to function correctly throughout all conditions.

Abstract: A video signal processing system with a dynamic calibration loop of an ADC comprises a calibration switch for transmitting signals according to a control signal; a reference switch module for transmitting reference voltages according to a plurality of control signals; a reference voltage generator coupled to the reference switch module for providing the reference voltages; a coarse tuner coupled to the calibration switch and the reference switch module for coarse-tuning received signals; an ADC coupled to the coarse tuner for converting analog signals to digital signals; a fine-tuner coupled to the ADC for fine-tuning received signals; and a calibration logic module for controlling the calibration switch, the reference switch module, the coarse tuner, the ADC, and the fine tuner according to signals outputted from the fine tuner, so as to compensate errors of the ADC.

Abstract: A frequency synthesizer that includes two fractional dividers, two noise-shaped quantizers, three integer dividers, a PLL, an algorithm embodied in control logic, and an adjustment means. The noise-shaped quantizers are used to quantize two fractional (fixed-point) values, derived from the divider control words, into time-varying values. The dividers and PLL are used to generate an output signal by means of multiplying a reference signal by the quotient of the divider control word values. Accordingly, the frequency synthesizer of the present invention can provide a very precise output clock, with the average output frequency being the input frequency multiplied by the quotient of the two divider control words, and with high jitter stability.

Abstract: The present invention provides a passive RFID chip with on-chip charge pumps for generating electrical power for the chip from radio frequencies. The passive RFID chip comprises an analog portion and a digital portion. The analog portion primarily comprises a voltage sensor and an AM data detector. The digital portion comprises a state machine digital logic controller. Incoming RF signals enter the chip via external antennas. The RF signals are converted into regulated DC signals by RF-DC converters with the voltage sensor. The RF-DC converters provide power for all the on-chip components and hence the chip does not require external power supply. The incoming RF signals are demodulated by demodulators and enter the AM data detector where the envelope transitions are detected. A voltage alarm is provided to ensure the voltage level does not drop below an operational level of the chip.

Abstract: A high-speed video signal processing system, which includes a reception end for receiving analog signals; a plurality of analog to digital converters coupled to the reception end for converting analog signals received from the reception end to digital signals according to control signals; and an interleaving controller coupled to the plurality of analog to digital converters for generating the control signals to selectively enable the plurality of analog to digital converters according to a predetermined sequence.

Abstract: A video signal processing system with a dynamic calibration loop of an ADC comprises a calibration switch for transmitting signals according to a control signal; a reference switch module for transmitting reference voltages according to a plurality of control signals; a reference voltage generator coupled to the reference switch module for providing the reference voltages; a coarse tuner coupled to the calibration switch and the reference switch module for coarse-tuning received signals; an ADC coupled to the coarse tuner for converting analog signals to digital signals; a fine-tuner coupled to the ADC for fine-tuning received signals; and a calibration logic module for controlling the calibration switch, the reference switch module, the coarse tuner, the ADC, and the fine tuner according to signals outputted from the fine tuner, so as to compensate errors of the ADC.

Abstract: A video scaling apparatus includes a receiver for receiving incoming video signals having transmitted therein a plurality of incoming frames, each incoming frame having a first plurality of synchronization signals for indicating lines in the incoming frame; a scaler with a line extender for generating outgoing video signals having transmitted therein a plurality of outgoing frames, each outgoing frame having a second plurality of synchronization signals for indicating lines in the outgoing frame, and for generating an outgoing frame for each incoming frame. The line extender ensures durations of all lines in the outgoing video signals are of substantially equal length. By ensuring that all lines in the outgoing frame are of substantially the same length, the reliability of a display device receiving the outgoing video signals is increased. Additionally, the frequency requirements of an outgoing clock for the video signals can be less stringent.