Abstract: An anti-fuse sensing circuit provided with no static current flowing in an anti-fuse sensing cell thereof. The sensing circuit comprises a switch and an inverter. The switch is operatively connected with an anti-fuse in series between a first power rail and a second power rail thereby forming a sensing node therebetween. The inverter is configured with an input operatively connected to the sensing node and an output operatively connected to the switch. Accordingly, the switch and the inverter constitute a feedback loop so as to sense that the anti-fuse is either un-programmed or programmed.

Abstract: The present invention provides a passive RFID chip with on-chip charge pumps for generating electrical power for the chip from radio frequencies. The passive RFID chip comprises an analog portion and a digital portion. The analog portion primarily comprises a voltage sensor and an AM data detector. The digital portion comprises a state machine digital logic controller. Incoming RF signals enter the chip via external antennas. The RF signals are converted into regulated DC signals by RF-DC converters with the voltage sensor. The RF-DC converters provide power for all the on-chip components and hence the chip does not require external power supply. The incoming RF signals are demodulated by demodulators and enter the AM data detector where the envelope transitions are detected. A voltage alarm is provided to ensure the voltage level does not drop below an operational level of the chip.

Abstract: A PLL architecture with fast phase acquisition, a stable freerun output frequency, and post-freerun fast phase recovery. The invention is particularly well suited for use in a video graphics a/d conversion circuit. An intelligent phase lock loop is optimized to determine the time difference between the closest rising edge of an PLL output signal and the rising edge of an input signal. The time difference in combination with the current PLL lock state determine an operational code used in a digital signal processing loop filter used to control a digitally controlled oscillator. The PLL also provides a stable output frequency during freerun periods, and a phase booster circuit for post-freerun fast phase recovery.

Abstract: The present invention provides a frequency synthesis circuit. The frequency synthesis circuit includes a noise-shaping quantizer and a digitally controlled oscillator. The noise-shaping quantizer responsive to a plurality of input bits for shaping error signals resulting from the quantization conversion such that most of the error occurs at high frequency. The digitally controlled oscillator is connected to the output of the quantizer having an output frequency responsive to the output of the quantizer.