Patents by Inventor Steve S. Chiang

Steve S. Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7671428
    Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: March 2, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Satyadev R. Patel, Andrew G. Huibers, Steve S. Chiang
  • Patent number: 7655492
    Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: February 2, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Satyadev R. Patel, Andrew G. Huibers, Steve S. Chiang
  • Patent number: 7586668
    Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: September 8, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Satyadev R. Patel, Andrew G. Huibers, Steve S. Chiang
  • Patent number: 7573111
    Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: August 11, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Satyadev R. Patel, Andrew G. Huibers, Steve S. Chiang
  • Patent number: 7449358
    Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: November 11, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Satyadev R. Patel, Andrew G. Huibers, Steve S. Chiang
  • Patent number: 7286278
    Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: October 23, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Satyadev R. Patel, Andrew G. Huibers, Steve S. Chiang
  • Patent number: 7198982
    Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: April 3, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Satyadev R. Patel, Andrew G. Huibers, Steve S. Chiang
  • Patent number: 6995034
    Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: February 7, 2006
    Assignee: Reflectivity, INC
    Inventors: Satyadev R. Patel, Andrew G. Huibers, Steve S. Chiang
  • Patent number: 6995040
    Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: February 7, 2006
    Assignee: Reflectivity, Inc
    Inventors: Satyadev R. Patel, Andrew G. Huibers, Steve S. Chiang
  • Patent number: 6603187
    Abstract: The present invention relates to a high performance, high reliability antifuse using conductive electrodes. According to first and second embodiments, the problem of switch-off in conductor-to-conductor antifuses is solved by utilizing conductive electrode materials having a relatively lower thermal conductivity than prior art electrode materials and by utilizing relatively thin electrodes, thus increasing their thermal resistance. According to a third embodiment, a relatively thin barrier layer is placed between one or both of the low thermal conductivity electrodes and the antifuse material to prevent reaction between the conductive electrodes and the antifuse material, or the materials used in manufacturing. According to a fourth embodiment, low thermal conductivity conductors are used for both electrodes in the conductor-to-conductor antifuse to achieve enhanced reliability and freedom from switch-off.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: August 5, 2003
    Assignee: Actel Corporation
    Inventors: Guobiao Zhang, Chenming Hu, Steve S. Chiang
  • Patent number: 6111302
    Abstract: The present invention relates to a high performance, high reliability antifuse using conductive electrodes. The problem of switch-off of the programmed antifuses is solved by reducing the thermal conductivity of the conductive electrodes. This is achieved by using lower thermal conductivity conductors for the electrodes or by using thinner electrodes to increase thermal resistance. According to a first aspect of the present invention, the problem of switch-off in conductor-to-conductor antifuses is solved by utilizing conductive electrode materials having a relatively lower thermal conductivity than prior art electrode materials. According to a second aspect of the present invention, the problem of switch-off in conductor-to-conductor antifuses is solved by utilizing relatively thin electrodes, thus increasing their thermal resistance.
    Type: Grant
    Filed: August 30, 1995
    Date of Patent: August 29, 2000
    Assignee: Actel Corporation
    Inventors: Guobiao Zhang, Chenming Hu, Steve S. Chiang
  • Patent number: 6034427
    Abstract: An integrated circuit (IC) package substrate has a dielectric layer and a micro filled via formed substantially in the center of a hole in the dielectric layer. The IC package substrate has at least one chip bonding pad and one ball attach pad that are electrically coupled to each other by the micro filled via. The micro filled via is formed of a material called a "micro filled via material" that includes a binding material and optionally includes a number of particles (between 0%-90% by volume) dispersed in the binding material. The binding material can be any material, such as a polymer that is either conductive or nonconductive. The particles can be formed of any conductive material, such as a conductive polymer or a conductive metal (e.g. copper or gold). An electrical conductor can be originally formed simply by contact between conductive particles located adjacent to each other.
    Type: Grant
    Filed: January 28, 1998
    Date of Patent: March 7, 2000
    Assignee: Prolinx Labs Corporation
    Inventors: James J. D. Lan, Steve S. Chiang, Paul Y. F. Wu, William H. Shepherd, John Y. Xie, Hang Jiang
  • Patent number: 5987744
    Abstract: A structure includes a support layer formed of a conductive material, such as a sheet of copper. The support layer has a number of conductive islands isolated from other portions of the support layer by isolation gaps. The support layer is sandwiched between two compound layers each of which is formed of a dielectric layer having a number of via holes and conductive elements located in the via holes. The conductive elements are formed at predetermined locations such that a conductive element in each compound layer contacts a conductive island in the support layer. The structure also includes two conductive layers formed on the two respective compound layers such that a trace in a first conductive layer is coupled to a trace in a second conductive layer through two conductive elements in the respective two compound layers and an island in the support layer. Such a structure can be formed by a number of processes.
    Type: Grant
    Filed: July 1, 1997
    Date of Patent: November 23, 1999
    Assignee: Prolinx Labs Corporation
    Inventors: James J. D. Lan, Steve S. Chiang, Paul Y. F. Wu, John Y. Xie
  • Patent number: 5962815
    Abstract: A multilayered structure, such as a printed circuit board, includes a first conductive layer and a second conductive layer that are separated from each other by a dielectric layer. The dielectric layer is formed of a first material, such as a photoimagible polyimide and epoxy resin. The dielectric layer has a number of via holes that extend from the first conductive layer to the second conductive layer. The via holes are filled with a second material having a breakdown voltage less than a breakdown voltage of the first material included in the dielectric layer to form an antifuse. The second material in the via holes can be, for example, a conductive epoxy resin or a polymer loaded with conductive particles (also referred to as "conductive paste").
    Type: Grant
    Filed: January 18, 1995
    Date of Patent: October 5, 1999
    Assignee: Prolinx Labs Corporation
    Inventors: James J. D. Lan, Steve S. Chiang, William H. Shepherd, Paul Y. F. Wu
  • Patent number: 5917229
    Abstract: Two types of programmable elements, fuses and antifuses, are disclosed for interconnecting the terminals of electronic components mounted on printed circuit boards (PCBs), multichip modules (MCMs) or in integrated circuit packages (IC packages). Both types of programmable elements can be fabricated as part of the regular processes used to fabricate PCBs, MCMs, or IC package (pin grid array). For fuses and antifuses, the material, geometry and dimensions can be varied to minimize the real estate and maximize programming efficiency (reduce programming time). Each type of programmable element, fuse or antifuse, can be separately used in matrices to form programmable board and package substrates. When both types of programmable elements are used together, more efficient placement and route architectures take advantage of the characteristics of each type of programmable element. Furthermore, combinations of both fuses and antifuses in the same structure allows the architecture to be reprogrammable.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: June 29, 1999
    Assignee: Prolinx Labs Corporation
    Inventors: Richard J. Nathan, James J. D. Lan, Steve S. Chiang
  • Patent number: 5906043
    Abstract: In one embodiment, the steps for forming an electrical conductor between conductive layers of a printed circuit board include the following steps: (1) applying a first dielectric material on a first conductive layer; (2) forming a number of via holes at each of the predetermined locations in the first dielectric material at which an electrical conductor is to be formed; (3) selectively applying a second dielectric material to at least fill each of the via holes, to form a composite dielectric layer; (4) applying a second conductive layer on the composite dielectric layer; (5) etching the first conductive layer to form a first electrode; (6) etching the second conductive layer to form a second electrode; and (7) applying a programming voltage across the second dielectric material in each of the via holes to form an electrical conductor in each of the via holes, each electrical conductor connecting an electrode in the first conductive layer to an electrode in the second conductive layer.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: May 25, 1999
    Assignee: Prolinx Labs Corporation
    Inventors: James J. D. Lan, Steve S. Chiang, William H. Shepherd, Paul Y. F. Wu
  • Patent number: 5906042
    Abstract: A micro filled material includes a binding material and optionally includes a number of particles. The binding material and the particles can be formed of any conductive or nonconductive material. Using such a micro filled via material, an electrical conductor is formed in a substrate for supporting one or more electronic components using the following steps: placing the micro filled via material between two conductive layers at various locations in a substrate at which an electrical conductor is to be formed; and optionally programming the micro filled via material to reduce the resistance of, or to form an electrical conductor.
    Type: Grant
    Filed: October 4, 1995
    Date of Patent: May 25, 1999
    Assignee: Prolinx Labs Corporation
    Inventors: James J. D. Lan, Steve S. Chiang, William H. Shepherd, Paul Y. F. Wu, John Y. Xie
  • Patent number: 5872338
    Abstract: A structure includes a support layer formed of a conductive material, such as a sheet of copper. The support layer has a number of conductive islands isolated from other portions of the support layer by isolation gaps. The support layer is sandwiched between two compound layers each of which is formed of a dielectric layer having a number of via holes and conductive elements located in the via holes. The conductive elements are formed at predetermined locations such that a conductive element in each compound layer contacts a conductive island in the support layer. The structure also includes two conductive layers formed on the two respective compound layers such that a trace in a first conductive layer is coupled to a trace in a second conductive layer through two conductive elements in the respective two compound layers and an island in the support layer. Such a structure can be formed by a number of processes.
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: February 16, 1999
    Assignee: Prolinx Labs Corporation
    Inventors: James J. D. Lan, Steve S. Chiang, Paul Y. F. Wu, John Y. Xie
  • Patent number: 5856234
    Abstract: An antifuse fabrication process includes the steps of forming a lower antifuse electrode, forming an insulating layer over the lower antifuse electrode, forming an antifuse aperture in the insulating layer, forming a dielectric antifuse material including a first layer comprising silicon dioxide and a second layer comprising silicon nitride over the antifuse insulating layer, etching the silicon nitride layer to form a small layer of silicon nitride in a region centered over the antifuse aperture, optionally forming a third dielectric antifuse layer comprising silicon dioxide, and forming an upper antifuse electrode. Alternatively, the first, second, and third layers of dielectric antifuse material may be formed and then etched to form a small composite sandwich structure of silicon nitride and silicon dioxide over the first silicon dioxide layer in a region centered over the antifuse aperture prior to forming an upper antifuse electrode.
    Type: Grant
    Filed: July 11, 1995
    Date of Patent: January 5, 1999
    Assignee: Actel Corporation
    Inventors: Steve S. Chiang, Wenn-Jei Chen
  • Patent number: 5834824
    Abstract: A novel antifuse includes a composite of conductive particles dispersed throughout a nonconductive matrix, which composite is located inside an antifuse via. The antifuse via is defined by a dielectric layer that separates two electrodes. The electrodes can be located in the same conductive layer plane (typically parallel to and isolated from one another) or in two different conductive planes (typically formed transverse to one another and separated by a dielectric with an antifuse via formed therein). The electrodes can be coupled to, for example, active or passive regions of the integrated circuit. One embodiment of an antifuse (also called "composite antifuse") has only the composite in an antifuse via between the two conductive layers. Another embodiment of an antifuse (also called "hybrid antifuse") includes in addition to the composite, one or more thin dielectric layers also located in the antifuse via between the two conductive layers.
    Type: Grant
    Filed: March 14, 1995
    Date of Patent: November 10, 1998
    Assignee: Prolinx Labs Corporation
    Inventors: William H. Shepherd, Steve S. Chiang, John Y. Xie