Abstract: A method and apparatus is provided for determining a measurement of a portion of a load in a basket that is rotatably supported provided, the method includes: a) determining, a dry load measurement; b) spinning, the basket that is rotatably supported in order to gradually remove the liquid from the load, wherein the liquid is removed substantially by centrifugal force on the basket that is rotatably supported; c) determining a wet load measurement, wherein the dry load measurement is less than the wet load measurement; d) comparing the dry load measurement to the wet load measurement to determine a remaining liquid measurement; and e) repeating c) and d) until the remaining liquid measurement substantially is within a predetermined percentage threshold of about 0 percent to about 50 percent of the wet load measurement.

Abstract: A method of operating a motor, the method comprising: operating a motor at a first speed; operating the motor in negative slip; imbalancing at least one phase of the motor to dissipate regeneration energy using windings of the motor; and wherein a next motor speed is decreased to a speed less than the first speed. An apparatus for carrying out the method is also presented.

Abstract: A washing machine is provided that includes measuring a load in a washer with a motor, the method comprising: a) accelerating a load in the washer b) providing a first input voltage and running the motor until a first speed of the motor is stable; c) providing a second input voltage, d) starting a timer, upon providing the second input voltage, and obtaining a first time measurement; e) operating the motor until the load speed responds to the second input voltage to the motor and is stable; f) stopping the timer and obtaining a second time measurement; g) calculating a time differential between the first time measurement and the second time measurement; and h) determining the load size using a load size equation and the time differential.

Abstract: An apparatus for air-cooling an electronic device is disclosed. A contoured panel channels a flow of air within the housing of an electronic device so as to channel the flow of air more directly over heat producing elements such as the microprocessor and peripheral cards. A sensor can also be employed to determine whether the panel is present and properly placed. If not, measures can be taken to reduce the heat generated by the heat producing elements. For example, a warning can be displayed, or the microprocessor can be instructed to enter sleep mode.

Abstract: Structures for memory devices. The structure includes (a) a substrate; (b) a first and second electrode regions on the substrate; and (c) a third electrode region disposed between the first and second electrode regions. In response to a first write voltage potential applied between the first and third electrode regions, the third electrode region changes its own shape, such that in response to a pre-specified read voltage potential subsequently applied between the first and third electrode regions, a sensing current flows between the first and third electrode regions. In addition, in response to a second write voltage potential being applied between the second and third electrode regions, the third electrode region changes its own shape such that in response to the pre-specified read voltage potential applied between the first and third electrode regions, said sensing current does not flow between the first and third electrode regions.

Abstract: A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.

Abstract: A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The completed device structure includes a gate electrode with a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.

Abstract: Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes shallow trench isolation filled with liquid phase deposited silicon dioxide (LPD-SiO2). The shallow trench isolation region is used to isolate two active regions formed on a silicon-on-insulator (SOI) substrate. By selectively depositing the oxide so that the active areas are not covered with the oxide, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.

Abstract: A method and structure for forming a semiconductor structure. A semiconductor substrate is provided. A trench is formed within the semiconductor substrate. A first layer of electrically insulative material is formed within the trench. A first portion and a second portion of the first layer of electrically insulative material is removed. A second layer of electrically insulative material is selectively grown on the first layer comprising the removed first portion and the removed second portion.

Abstract: A novel arrangement and method for depositing evaporation control agents so as to coat immersion lithographic solutions which are employed on the surface of semiconductor wafers in connection with the etching of the surfaces of the wafer through the intermediary of an immersion lithographic process.

Abstract: According to embodiments, a beam scanning system such as a scanned beam display or scanned beam image capture system includes a controller having a PLL circuit that is operable to track systematic variations in fast scan frequency, such as those that are a function of slow scan angle. The controller is further operable to modify video clocking to compensate for the systematic variations in fast scan phase as a function of slow scan angle.

Abstract: A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.

Abstract: An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid.

Abstract: A port adapter for connecting zero or more network interfaces to a host system having a SPI-4 bus is disclosed. The port adapter comprises zero or more network interfaces; a SPI-4 bus coupled to a host system to provide a communication channel between the host and the network interfaces; a control bus coupled to the host system for controlling and monitoring the port adapter; and interface logic that interfaces the SPI-4 bus and the control bus to the network interfaces. Methods are provided for selecting and using one of a small plurality of different packet formats for various networking technologies, so that the port adapter can hide details of the technology that it handles from the host system, and for operating the host system's SPI-4 bus at one of several speeds based on bandwidth requirements of the port adapter.

Abstract: A fuse structure and a method for operating the same. The fuse structure operating method includes providing a structure. The structure includes (a) an electrically conductive layer and (b) N electrically conductive regions hanging over without touching the electrically conductive layer. N is a positive integer and N is greater than 1. The N electrically conductive regions are electrically connected together. The structure operating method further includes causing a first electrically conductive region of the N electrically conductive regions to touch the electrically conductive layer without causing the remaining N?1 electrically conductive regions to touch the electrically conductive layer.

Abstract: Quick release couplings for releasably coupling components of a computer to the computer are disclosed. The quick release coupling mechanisms are generally configured to allow tool-less placement of the components relative to the computer. That is, the quick release coupling mechanisms are configured to perform their couplings without using conventional fasteners such as screws, bolts, etc. By eliminating the use of fasteners, the components may be inserted and removed from the computer without using tools (e.g., tool-less). Furthermore, the quick release couplings are easy to maneuver thereby enabling quick and straightforward assembly and disassembly of the components to and from the computer (e.g., quick release). For example, the components may be inserted and removed by a simple pushing or pulling motion, and/or by a simple flick of a latch or handle.

Abstract: Disclosed are a semiconductor structure and a method that allow for simultaneous voltage/current conditioning of multiple memory elements in a nonvolatile memory device with multiple memory cells. The structure and method incorporate the use of a resistor connected in series with the memory elements to limit current passing through the memory elements. Specifically, the method and structure incorporate a blanket temporary series resistor on the wafer surface above the memory cells and/or permanent series resistors within the memory cells. During the conditioning process, these resistors protect the transition metal oxide in the individual memory elements from damage (i.e., burn-out), once it has been conditioned.

Abstract: A method of fabricating a structure and fabricating related semiconductor transistors and novel semiconductor transistor structures. The method of fabricating the structure includes: providing a substrate having a top surface; forming an island on the top surface of the substrate, a top surface of the island parallel to the top surface of the substrate, a sidewall of the island extending between the top surface of the island and the top surface of the substrate; forming a plurality of carbon nanotubes on the sidewall of the island; and performing an ion implantation, the ion implantation penetrating into the island and blocked from penetrating into the substrate in regions of the substrate masked by the island and the carbon nanotubes.

Abstract: To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.

Abstract: Micro-valves and micro-pumps and methods of fabricating micro-valves and micro-pumps. The micro-valves and micro-pumps include electrically conductive diaphragms fabricated from electrically conductive nano-fibers. Fluid flow through the micro-valves and pumping action of the micro-pumps is accomplished by applying electrostatic forces to the electrically conductive diaphragms.