Patents by Inventor Steven Leslie Pope
Steven Leslie Pope has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11983133Abstract: An integrated circuit device includes multiple heterogeneous functional circuit blocks and interface circuitry that permits the heterogeneous functional circuit blocks to exchange data with one another using communication protocols of the respective heterogeneous functional circuit blocks. The IC device includes fixed-function circuitry, user-configurable circuitry (e.g., programmable logic), and/or embedded processors/cores. A functional circuit block may be configured in fixed-function circuitry or in the user-configurable circuitry (i.e., as a plug-in). The interface circuitry includes a network-on-a-chip (NoC), an adaptor configured in the user-configurable circuitry, and/or memory. The memory may be accessible to the functional circuit blocks through an adaptor configured the user-configurable circuitry and/or through the NoC. The IC device may be configured as a SmartNIC, DPU, or other type of system-on-a-chip (SoC).Type: GrantFiled: August 22, 2022Date of Patent: May 14, 2024Assignee: XILINX, INC.Inventors: Jaideep Dastidar, David James Riddoch, Steven Leslie Pope
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Patent number: 11966351Abstract: A network interface device comprises a streaming data processing path comprising a first data processing engine and hubs. A first scheduler associated with a first hub controls an output of data by the first hub to the first data processing engine and a second scheduler associated with a second hub controls an output of data by the second hub. The first hub is arranged upstream of the first data processing engine on the data processing path and is configured to receive data from a first upstream data path entity and from a first data processing entity implemented in programmable circuitry via a data ingress interface of the first hub. The first data processing engine is configured to receive data from the first hub, process the received data and output the processed data to the second hub arranged downstream of first data processing engine.Type: GrantFiled: March 11, 2021Date of Patent: April 23, 2024Assignee: XILINX, INC.Inventors: Steven Leslie Pope, Derek Edward Roberts, Dmitri Kitariev, Neil Duncan Turton, David James Riddoch, Ripduman Sohan
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Patent number: 11960596Abstract: A network interface device comprises a first area of trust comprising a first part of the network interface device, the first part comprising one or more first kernels. A second area of trust comprising a second part of the network interface device different to said first part is provided, the second part comprising one or more second kernels. A communication link is provided between the first area of trust and the second area of trust. At least one of the first and second areas of trust is provided with isolation circuitry configured to control which data which is passed to the other of the first and second areas via the communication link.Type: GrantFiled: March 11, 2021Date of Patent: April 16, 2024Assignee: XILINX, INC.Inventors: Steven Leslie Pope, Derek Edward Roberts, Dmitri Kitariev, Neil Duncan Turton, David James Riddoch, Ripduman Sohan
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Patent number: 11924032Abstract: A network interface device comprises a plurality of components configured to process a flow of data one after another. A control component is configured to provide one or more control messages in said flow, said one or more control message being provided to said plurality of components one after another such that a configuration of one or more of said components is changed.Type: GrantFiled: November 23, 2021Date of Patent: March 5, 2024Assignee: Xilinx, Inc.Inventors: Steven Leslie Pope, David James Riddoch
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Publication number: 20240061799Abstract: An integrated circuit device includes multiple heterogeneous functional circuit blocks and interface circuitry that permits the heterogeneous functional circuit blocks to exchange data with one another using communication protocols of the respective heterogeneous functional circuit blocks. The IC device includes fixed-function circuitry, user-configurable circuitry (e.g., programmable logic), and/or embedded processors/cores. A functional circuit block may be configured in fixed-function circuitry or in the user-configurable circuitry (i.e., as a plug-in). The interface circuitry includes a network-on-a-chip (NoC), an adaptor configured in the user-configurable circuitry, and/or memory. The memory may be accessible to the functional circuit blocks through an adaptor configured the user-configurable circuitry and/or through the NoC. The IC device may be configured as a SmartNIC, DPU, or other type of system-on-a-chip (SoC).Type: ApplicationFiled: August 22, 2022Publication date: February 22, 2024Inventors: Jaideep DASTIDAR, David James RIDDOCH, Steven Leslie POPE
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Patent number: 11824830Abstract: A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is provide to assign different processing stages to each processing unit. A controller is provided to switch between different processing circuitry on the fly so that one processing circuitry may be used whilst another is being compiled.Type: GrantFiled: April 30, 2021Date of Patent: November 21, 2023Assignee: Xilinx, Inc.Inventors: Steven Leslie Pope, Neil Turton, David James Riddoch, Dmitri Kitariev, Ripduman Sohan, Derek Edward Roberts
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Patent number: 11726928Abstract: A network interface device has a data source, a data sink and an interconnect configured to receive data from the data source and to output data to the data sink. The interconnect has a memory having memory cells. Each memory cell has a width which matches a bus segment width. The memory is configured to receive a first write output with a width corresponding to the bus segment width. The write output comprises first data to be written to a first memory cell of the memory, the first data being from the data source.Type: GrantFiled: June 24, 2021Date of Patent: August 15, 2023Assignee: XILINX, INC.Inventors: Steven Leslie Pope, Derek Edward Roberts, Dmitri Kitariev, Neil Duncan Turton, David James Riddoch, Ripduman Sohan
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Publication number: 20230222082Abstract: Embodiments herein describe end-to-end bindings to create zones that extend between different components in a SoC, such as an I/O gateway, a processor subsystem, a NoC, storage and data accelerators, programmable logic, etc. Each zone can be assigned to a different domain that is controlled by a tenant such as an external host, or software executing on that host. Embodiments herein create end-to-end bindings between acceleration engines, I/O gateways, and embedded cores in SoCs. Instead of these components being treated as disparate monolithic components, the bindings divide up the hardware and memory resources across components that make up the SoC, into different zones. Those zones in turn can have unique bindings to multiple tenants. The bindings can be configured in bridges between components to divide resources into the zones to enable tenants of those zones to have dedicated available resources that are secure from the other tenants.Type: ApplicationFiled: January 12, 2022Publication date: July 13, 2023Inventors: Jaideep DASTIDAR, David James RIDDOCH, Steven Leslie POPE
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Publication number: 20230224261Abstract: A network interface device has data path circuitry configured to cause data to be moved into and/or out of the network interface device. The data path circuitry comprises: first circuitry for providing one or more data processing operations; and interface circuitry supporting channels. The channels comprises command channels receiving command information from a plurality of data path circuitry user instances, event channels providing respective command completion information to the plurality of data path user instances; and data channels providing the associated data.Type: ApplicationFiled: January 7, 2022Publication date: July 13, 2023Inventors: Steven Leslie POPE, Derek Edward ROBERTS, Dmitri KITARIEV, Neil Duncan TURTON, David James RIDDOCH, Ripduman SOHAN, Stephan DIESTELHORST
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Patent number: 11689648Abstract: A network interface device comprises an input configured to receive a storage response comprising a plurality of packets of data, one or more packets comprising a header part and data to be stored, the header part comprising a transport protocol header and a data storage application header. A first packet processor is configured to receive two or more of said plurality of packets and perform transport protocol processing of the received packets to provide transport protocol processed packets A second packet processor configured to receive the transport protocol processed packets from the first packet processor, to write the data to be stored of the received packets to memory and to provide the data storage application header and a pointer to a location in the memory to which the data has been written.Type: GrantFiled: March 11, 2021Date of Patent: June 27, 2023Assignee: XILINX, INC.Inventors: Steven Leslie Pope, Derek Edward Roberts, Dmitri Kitariev, Neil Duncan Turton, David James Riddoch, Ripduman Sohan
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Patent number: 11570045Abstract: A network interface device comprises a plurality of components configured to process a flow of data one after another. A control component is configured to provide one or more control messages in said flow, said one or more control message being provided to said plurality of components one after another such that a configuration of one or more of said components is changed.Type: GrantFiled: September 28, 2018Date of Patent: January 31, 2023Assignee: Xilinx, Inc.Inventors: Steven Leslie Pope, David James Riddoch
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Publication number: 20220414028Abstract: A network interface device has a data source, a data sink and an interconnect configured to receive data from the data source and to output data to the data sink. The interconnect has a memory having memory cells. Each memory cell has a width which matches a bus segment width. The memory is configured to receive a first write output with a width corresponding to the bus segment width. The write output comprises first data to be written to a first memory cell of the memory, the first data being from the data source.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Inventors: Steven Leslie POPE, Derek Edward ROBERTS, Dmitri KITARIEV, Neil Duncan TURTON, David James RIDDOCH, Ripduman SOHAN
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Patent number: 11537541Abstract: A network interface device comprises a plurality of components configured to process a flow of data one after another. A control component is configured to provide one or more control messages in said flow, said one or more control message being provided to said plurality of components one after another such that a configuration of one or more of said components is changed.Type: GrantFiled: July 15, 2019Date of Patent: December 27, 2022Assignee: Xilinx, Inc.Inventors: Steven Leslie Pope, David James Riddoch
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Publication number: 20220292184Abstract: A network interface device comprises a first area of trust comprising a first part of the network interface device, the first part comprising one or more first kernels. A second area of trust comprising a second part of the network interface device different to said first part is provided, the second part comprising one or more second kernels. A communication link is provided between the first area of trust and the second area of trust. At least one of the first and second areas of trust is provided with isolation circuitry configured to control which data which is passed to the other of the first and second areas via the communication link.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Inventors: Steven Leslie POPE, Derek Edward ROBERTS, Dmitri KITARIEV, Neil Duncan TURTON, David James RIDDOCH, Ripduman SOHAN
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Publication number: 20220292042Abstract: A network interface device comprises a streaming data processing path comprising a first data processing engine and hubs. A first scheduler associated with a first hub controls an output of data by the first hub to the first data processing engine and a second scheduler associated with a second hub controls an output of data by the second hub. The first hub is arranged upstream of the first data processing engine on the data processing path and is configured to receive data from a first upstream data path entity and from a first data processing entity implemented in programmable circuitry via a data ingress interface of the first hub. The first data processing engine is configured to receive data from the first hub, process the received data and output the processed data to the second hub arranged downstream of first data processing engine.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Inventors: Steven Leslie POPE, Derek Edward ROBERTS, Dmitri KITARIEV, Neil Duncan TURTON, David James RIDDOCH, Ripduman SOHAN
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Publication number: 20220294883Abstract: A network interface device comprises an input configured to receive a storage response comprising a plurality of packets of data, one or more packets comprising a header part and data to be stored, the header part comprising a transport protocol header and a data storage application header. A first packet processor is configured to receive two or more of said plurality of packets and perform transport protocol processing of the received packets to provide transport protocol processed packets A second packet processor configured to receive the transport protocol processed packets from the first packet processor, to write the data to be stored of the received packets to memory and to provide the data storage application header and a pointer to a location in the memory to which the data has been written.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Inventors: Steven Leslie POPE, Derek Edward ROBERTS, Dmitri KITARIEV, Neil Duncan TURTON, David James RIDDOCH, Ripduman SOHAN
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Patent number: 11429438Abstract: A network interface device has an input configured to receive data from a network. The data is for one of a plurality of different applications. The network interface device also has at least one processor configured to determine which of a plurality of available different caches in a host system the data is to be injected by accessing to a receive queue comprising at least one descriptor indicating a cache location in one of said plurality of caches to which data is to be injected, wherein said at least one descriptor, which indicates the cache location, has an effect on subsequent descriptors of said receive queue until a next descriptor indicates another cache location. The at least one processor is also configured to cause the data to be injected to the cache location in the host system.Type: GrantFiled: October 13, 2020Date of Patent: August 30, 2022Assignee: Xilinx, Inc.Inventors: Steven Leslie Pope, David James Riddoch
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Patent number: 11321150Abstract: A method and data processing system are provided. The data processing system comprises an application associated with a plurality of sockets and a sub-system for making data available to the application via the plurality of sockets. The sub-system is configured to provide in response to a request from the application: an indication of events that have occurred on one or more of the plurality of sockets; and an indication of an order in which the events should be processed.Type: GrantFiled: August 14, 2019Date of Patent: May 3, 2022Assignee: Xilinx, Inc.Inventors: Steven Leslie Pope, David James Riddoch, Kieran Mansley, Sian Cathryn James
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Publication number: 20220086042Abstract: A network interface device comprises a plurality of components configured to process a flow of data one after another. A control component is configured to provide one or more control messages in said flow, said one or more control message being provided to said plurality of components one after another such that a configuration of one or more of said components is changed.Type: ApplicationFiled: November 23, 2021Publication date: March 17, 2022Applicant: Xilinx, Inc.Inventors: Steven Leslie Pope, David James Riddoch
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Patent number: 11245580Abstract: A network interface device comprises a plurality of components configured to process a flow of data one after another. A control component is configured to provide one or more control messages in said flow, said one or more control message being provided to said plurality of components one after another such that a configuration of one or more of said components is changed.Type: GrantFiled: September 28, 2018Date of Patent: February 8, 2022Assignee: Xilinx, Inc.Inventors: Steven Leslie Pope, David James Riddoch