Patents by Inventor Steven M Bennett

Steven M Bennett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8533428
    Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: September 10, 2013
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard Uhlig, Larry Smith, Dion Rodgers
  • Publication number: 20130232488
    Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 5, 2013
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Dion Rodgers, Richard A. Uhlig, Lawrence O. Smith, Barry E. Huntley
  • Publication number: 20130219143
    Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.
    Type: Application
    Filed: March 15, 2013
    Publication date: August 22, 2013
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard UhligQ, Lawrence Smith, III, Scott D. Rodgers
  • Publication number: 20130067184
    Abstract: According to an embodiment of the invention, a method for operating a data processing machine is described in which data about a state of the machine is written to a location in storage. The location is one that is accessible to software that may be written for the machine. The state data as written is encoded. This state data may be recovered from the storage according to a decoding process. Other embodiments are also described and claimed.
    Type: Application
    Filed: March 6, 2012
    Publication date: March 14, 2013
    Inventors: Scott H. Robinson, Gustavo P. Espinosa, Steven M. Bennett
  • Publication number: 20130054935
    Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
    Type: Application
    Filed: October 23, 2012
    Publication date: February 28, 2013
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard Uhlig, Dion Rodgers, Rajesh M. Sankaran, Camron Rust, Sebastian Schoenberg
  • Patent number: 8370559
    Abstract: Embodiments of apparatuses, methods, and systems for executing a protected device model in a virtual machine are disclosed. In one embodiment, an apparatus includes recognition logic, memory management logic, control logic, and execution logic. The recognition logic is to recognize an indication, during execution of first code on a virtual machine, that the first code is attempting to access a device. The memory management logic is to prevent the virtual machine from accessing a portion of memory during execution of the first code, and to allow the virtual machine to access the portion of memory in response to the indication. The control logic is to transfer control of the apparatus from the first code to second code stored in the portion of memory, without exiting the virtual machine. The execution logic is to execute the second code to model the device.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: February 5, 2013
    Assignee: Intel Corporation
    Inventors: Sebastian Schoenberg, Steven M. Bennett, Andrew V. Anderson
  • Publication number: 20130024861
    Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.
    Type: Application
    Filed: August 27, 2012
    Publication date: January 24, 2013
    Applicant: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Dion Rodgers, Richard A. Uhlig, Lawrence O. Smith, Barry E. Huntley
  • Publication number: 20120331467
    Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.
    Type: Application
    Filed: September 6, 2012
    Publication date: December 27, 2012
    Inventors: Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard A. Uhlig, Udo Steinberg, Sebastian Schoenberg, Sridhar Muthrasanallur, Steven M. Bennett, Andrew V. Anderson, Erik C. Cota-Robles
  • Publication number: 20120317572
    Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.
    Type: Application
    Filed: August 20, 2012
    Publication date: December 13, 2012
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Dion Rodgers, Richard A. Uhlig, Lawrence O. Smith, Barry E. Huntley
  • Patent number: 8296546
    Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: October 23, 2012
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard Uhlig, Dion Rodgers, Rajesh M Sankaran, Camron Rust, Sebastian Schoenberg
  • Patent number: 8291410
    Abstract: Embodiments of apparatuses, methods, and systems for controlling virtual machines based on activity state are disclosed. In one embodiment, an apparatus includes virtual machine entry logic and activity state evaluation logic. The virtual machine entry logic is to transfer control of the apparatus from a host to a guest. The activity state evaluation logic is to determine whether the activity state of the guest would be inactive upon receiving control.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: October 16, 2012
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Dion Rodgers, Barry E. Huntley, Lawrence O. Smith, Shashank Shekhar
  • Patent number: 8286162
    Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: October 9, 2012
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard A. Uhlig, Udo Steinberg, Sebastian Schoenberg, Sridhar Muthrasanallur, Steven M. Bennett, Andrew V. Anderson, Erik C. Cota-Robles
  • Patent number: 8271978
    Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: September 18, 2012
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Dion Rodgers, Richard A. Uhlig, Lawrence O. Smith, Barry E. Huntley
  • Patent number: 8230203
    Abstract: Embodiments of apparatuses, methods, and systems detecting spin loops in a virtual machine environment are disclosed. In one embodiment, an apparatus includes detection logic and virtualization logic. The detection logic is to detect whether a guest is executing a spin loop. The virtualization logic is to transfer control of the apparatus from the guest to a host in response to the detection logic detecting that the guest is executing the spin loop.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: July 24, 2012
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Randolph L. Campbell, James B. Crossland, Gideon Gerzon, Leena K. Puthiyedath, Stephen A. Fischer, Steven M. Bennett, Andrew V. Anderson
  • Publication number: 20120110299
    Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
    Type: Application
    Filed: January 11, 2012
    Publication date: May 3, 2012
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard Uhlig, Dion Rodgers, Rajesh Madukkaraumukumana, Camron Rust, Sebastian Schoenberg
  • Patent number: 8156343
    Abstract: According to an embodiment of the invention, a method for operating a data processing machine is described in which data about a state of the machine is written to a location in storage. The location is one that is accessible to software that may be written for the machine. The state data as written is encoded. This state data may be recovered from the storage according to a decoding process. Other embodiments are also described and claimed.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: April 10, 2012
    Assignee: Intel Corporation
    Inventors: Scott H. Robinson, Gustavo P. Espinosa, Steven M. Bennett
  • Patent number: 8151264
    Abstract: Embodiments of apparatuses, methods, and systems for injecting virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes virtual machine entry logic, recognition logic, and evaluation logic. The virtual machine entry logic is to initiate a transfer of control of the apparatus from a host to a guest running on a virtual machine. The recognition logic is to recognize a request from the host to inject a virtualization event into the virtual machine. The evaluation logic is to identify an intervening monitor to handle the virtualization event.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: April 3, 2012
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Dion Rodgers, Barry E. Huntley, Lawrence O. Smith
  • Publication number: 20120079481
    Abstract: In one embodiment, a predefined behavior of a virtual machine monitor (VMM) with respect to one or more virtual machines (VMs) is identified, and processor-managed resources associated with the one or more VMs are utilized based on the predefined behavior of the VMM.
    Type: Application
    Filed: November 7, 2011
    Publication date: March 29, 2012
    Inventors: STEVEN M. BENNETT, Andrew V. Anderson, Stalinselvaraj Jeyasingh, Alain Kagi, Gilbert Neiger, Richard Uhlig, Xiang Zou, Lawrence Smith, Scott Rodgers
  • Patent number: 8146078
    Abstract: In one embodiment, a method includes receiving a request to transition control to a virtual machine (VM) from a virtual machine monitor (VMM), calculating an offset value, receiving, during operation of the VM, a request for a current value of the timer, adjusting the current value of the timer based on the offset value, and providing the adjusted timer value to the VM.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: March 27, 2012
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Gilbert Neiger, Andrew V. Anderson
  • Patent number: 8099581
    Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: January 17, 2012
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard Uhlig, Dion Rodgers, Rajesh Madukkaraumukumana, Camron Rust, Sebastian Schoenberg