Abstract: In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing TCE data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of TCEs, and a number of levels in the TCE data structure is retained. In response to determining that the first real address range is not available for allocation, a second real address range discontiguous with the existing TCE data structure is allocated for storage of the TCEs, and a number of levels in the TCE data structure is increased.

Abstract: In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing TCE data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of TCEs, and a number of levels in the TCE data structure is retained. In response to determining that the first real address range is not available for allocation, a second real address range discontiguous with the existing TCE data structure is allocated for storage of the TCEs, and a number of levels in the TCE data structure is increased.

Abstract: Mechanisms for communicating with a network adapter using a queue data structure are provided. A device driver invokes device driver services for initializing address translation and protection table (ATPT) entries in a root complex for the queue data structure. The device driver services return untranslated addresses to the device driver which are in turn provided to the network adapter. In response to retrieving a queue element from the queue data structure, the network adapter may request a translation of an untranslated address specified in the queue element and store the translated address in the network adapter prior to receiving a data packet targeting a buffer associated with the queue element.

Abstract: In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing TCE data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of TCEs, and a number of levels in the TCE data structure is retained. In response to determining that the first real address range is not available for allocation, a second real address range discontiguous with the existing TCE data structure is allocated for storage of the TCEs, and a number of levels in the TCE data structure is increased.

Abstract: In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing TCE data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of TCEs, and a number of levels in the TCE data structure is retained. In response to determining that the first real address range is not available for allocation, a second real address range discontiguous with the existing TCE data structure is allocated for storage of the TCEs, and a number of levels in the TCE data structure is increased.

Abstract: In an embodiment, a north chip receives a secondary bus identifier that identifies a bus that is immediately downstream from a bridge in a south chip, a subordinate bus identifier that identifies a highest bus identifier of all of buses reachable downstream of the bridge, and an MMIO bus address range that comprises a memory base and a memory limit. The north chip writes a translation of a bridge identifier and a south chip identifier to the secondary bus identifier, the subordinate bus identifier, and the MMIO bus address range. The north chip sends the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit to the bridge. The bridge stores the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit in the bridge.

Abstract: In an embodiment, a south chip comprises a first virtual bridge connected to a shared egress port and a second virtual bridge also connected to the shared egress port. The first virtual bridge receives a first secondary bus identifier, a first subordinate bus identifier, and a first MMIO bus address range from a first north chip. The second virtual bridge receives a second secondary bus identifier, a second subordinate bus identifier, and a second MMIO bus address range from a second north chip. The first virtual bridge stores the first secondary bus identifier, the first subordinate bus identifier, and the first MMIO bus address range. The second virtual bridge stores the second secondary bus identifier, the second subordinate bus identifier, and the second MMIO bus address range. The first north chip and the second north chip are connected to the south chip via respective first and second point-to-point connections.

Abstract: In an embodiment, a translation of a hierarchical bus number to a physical bus number and a bridge identifier of a bridge are written to a north chip. A request is received that comprises an identifier of a destination. A determination is made that the identifier comprises the hierarchical bus number. In response to the determination, the identifier of the destination is replaced in the request with the physical bus number and the bridge identifier. The request is sent to the bridge identified by the bridge identifier. A south chip comprises the bridge, and the south chip is connected to the north chip via a point-to-point serial link. The physical bus number identifies a bus that connects the bridge to a device. The request comprises a configuration write request that requests a write of data to the device.

Abstract: A method, system and computer program product are provided for implementing PCI-Express memory domains for single root virtualized devices. A PCI host bridge (PHB) includes a memory mapped IO (MMIO) domain descriptor (MDD) and an MMIO Domain Table (MDT) are used to associate MMIO domains with PCI memory VF BAR spaces. One MDD is provided for each unique VF BAR space size per bus segment connecting a single root IO virtualization (SRIOV) device to the PCI host bridge (PHB). The MDT used with the MDD includes having a number of entries limited to a predefined total number of SRIOV VFs to be configured. A VF BAR Stride, which may be further implemented as a VF BAR Stride Capability Structure, is provided to reduce the number of MDDs required to map SRIOV VF BAR spaces. A particular definition of the MDD is provided to reduce the number of MDDs required to at most one per SRIOV bus segment below a PHB.

Abstract: In an embodiment, a north chip receives a secondary bus identifier that identifies a bus that is immediately downstream from a bridge in a south chip, a subordinate bus identifier that identifies a highest bus identifier of all of buses reachable downstream of the bridge, and an MMIO bus address range that comprises a memory base and a memory limit. The north chip writes a translation of a bridge identifier and a south chip identifier to the secondary bus identifier, the subordinate bus identifier, and the MMIO bus address range. The north chip sends the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit to the bridge. The bridge stores the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit in the bridge.

Abstract: A computer-implemented method may include determining that a slot coupled to a peripheral component interconnect host bridge is occupied by an input/output adapter. The computer-implemented method may include determining one or more characteristics of the input/output adapter and determining whether the input/output adapter is capable of using additional memory based on the one or more characteristics of the input/output adapter. The computer-implemented method may also include allocating the additional memory for the input/output adapter in response to determining that the input/output adapter is capable of using the additional memory.

Abstract: In an embodiment, a translation of a hierarchical MMIO address range to a physical MMIO address range and an identifier of a bridge in a south chip are written to a north chip. A transaction is received that comprises a hierarchical MMIO address. The hierarchical MMIO address that is within the hierarchical MMIO address range is replaced in the transaction with the identifier of the bridge and with a physical MMIO address that is within the physical MMIO address range in the south chip. The transaction is sent to the device that is connected to the bridge in the south chip. The physical MMIO address range specifies a range of physical MMIO addresses in memory in the device.

Abstract: Mechanisms are provided for implementing a multi-root PCI manager (MR-PCIM) in a multi-root I/O virtualization management partition (MR-IMP) to control the shared functionality of an multi-root I/O virtualization (IOV) enabled switch fabric and multi-root IOV enabled I/O adapter (IOA) through the base functions (BF) of the switches and IOAs. A hypervisor provides device-independent facilities to the code running in the I/O Virtualization Management Partition (IMP), Multi-Root (MR)-IMP and client partitions. The MR-IMP may include device specific code without the hypervisor needing to sacrifice its size, robustness, and upgradeability. The hypervisor provides the virtual intermediary functionally for the sharing and control of the switch and IOA's control functions.

Abstract: In one embodiment, a computer-implemented method for creating redundant system configurations is presented. The computer-implemented method creates a set of virtual function path authorization tables, and receives a request from a requester to provide requested data from a virtual function wherein the virtual function is performed by a single root or a multi-root peripheral component interconnect device. Further a receive buffer is created in a selected address range in a set of addresses ranges as well as a virtual function work queue entry for the virtual function containing an address of the receive buffer in the selected address range. Responsive to a determination that the virtual function is authorized, writing the requested data into the receive buffer of the selected address range in the one or more systems, and responsive to writing the requested data, issuing a notice of completion to the requester.

Abstract: In an embodiment a translation of RID (requester identifier) ranges to identifiers of north chips is stored into a south chip. A command that comprises a command RID is received at the south chip from a device. In response, a RID range is determined that encompasses the command RID, and a north chip identifier is found that is assigned a virtual function identified by the command RID. The command is sent from the south chip to the north chip identified by the north chip identifier. The translation comprises a RID compare value and a RID mask. A determination is made that the RID range encompasses the command RID by performing a logical-and operation on the command RID and the RID mask and comparing a result of the logical-and operation to the RID compare value.

Abstract: In an embodiment, a translation of a physical bus number to a hierarchical bus number is written to a south chip. The south chip receives a configuration write command that comprises a physical bus number. The south chip sends the configuration write command to a device via the bus identified by the physical bus number, and the device stores the physical bus number in the device. In response to a received message from a device that comprises the physical bus number, the south chip replaces the physical bus number in the message with the hierarchical bus number. The south chip sends the message to a north chip via a point-to-point serial link. Both the physical bus number and the hierarchical bus number identify a bus with which the device connects to a bridge in the south chip.

Abstract: A computer-implemented method may include determining that a slot coupled to a peripheral component interconnect host bridge is occupied by an input/output adapter. The computer-implemented method may include determining one or more characteristics of the input/output adapter and determining whether the input/output adapter is capable of using additional memory based on the one or more characteristics of the input/output adapter. The computer-implemented method may also include allocating the additional memory for the input/output adapter in response to determining that the input/output adapter is capable of using the additional memory.

Abstract: A mechanism for initializing shared memories for sharing endpoints across a plurality of root complexes is provided. A multi-root PCIe manager (MR-PCIM) initializes the shared memory between root complexes and endpoints by discovering the PCIe switch fabric by traversing all the links accessible through the interconnected switches of the PCIe switch fabric. As the links are traversed, the MR-PCIM compares information obtained for each of the root complexes and endpoints to determine which endpoints and root complexes reside on the same blade. A virtual PCIe tree data structure is then generated that ties the endpoints available on the PCIe switch fabric to each root complex. The MR-PCIM, or a single-root PCIe manager (SR-PCIM), may then assign each endpoint and root complex a base and limit within the PCIe memory address space the endpoint belongs to.

Abstract: In an embodiment, a command is received that requests movement of ownership of a target device from an origin compute element to a destination compute element. From the origin compute element, a translation of a virtual bridge identifier to a first secondary bus identifier, a first subordinate bus identifier, and a first MMIO bus address range is removed. To the destination compute element, a translation of the target virtual bridge identifier to a second secondary bus identifier, a second subordinate bus identifier, and a second MMIO bus address range is added. From a south chip that comprises the target virtual bridge, a translation of the target virtual bridge identifier to an identifier of the origin compute element is removed. To the south chip, a translation of the target virtual bridge identifier to an identifier of the destination compute element is added.

Abstract: A method, system and computer program product are provided for implementing PCI-Express memory domains for single root virtualized devices. A PCI host bridge (PHB) includes a memory mapped IO (MMIO) domain descriptor (MDD) and an MMIO Domain Table (MDT) are used to associate MMIO domains with PCI memory VF BAR spaces. One MDD is provided for each unique VF BAR space size per bus segment connecting a single root IO virtualization (SRIOV) device to the PCI host bridge (PHB). The MDT used with the MDD includes having a number of entries limited to a predefined total number of SRIOV VFs to be configured. A VF BAR Stride, which may be further implemented as a VF BAR Stride Capability Structure, is provided to reduce the number of MDDs required to map SRIOV VF BAR spaces. A particular definition of the MDD is provided to reduce the number of MDDs required to at most one per SRIOV bus segment below a PHB.